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400 lines
14 KiB
400 lines
14 KiB
(_flow fab_demo "2021.1-SP7"
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(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Aug 6 09:45:29 2024")
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(_version "1.0.5")
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(_status "initial")
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(_project
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)
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(_task tsk_setup
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(_widget wgt_select_arch
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(_input
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(_part
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(_family Logos)
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(_device PGL22G)
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(_speedgrade -6)
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(_package MBG324)
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(_file "source/src/zutils/zutils_clk_parser.v"
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(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
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(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
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(_timespec "2024-03-10T18:52:01")
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(_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
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(_timespec "2024-03-08T21:15:01")
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(_file "source/src/zutils/zutils_signal_filter_advance.v"
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(_format verilog)
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(_timespec "2024-03-08T21:15:01")
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(_file "source/src/zutils/zutils_freq_detector.v"
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(_format verilog)
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(_timespec "2024-03-10T17:37:01")
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(_format verilog)
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(_file "source/src/zutils/zutils_pwm_generator_v2.v"
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(_format verilog)
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(_timespec "2024-03-10T13:37:24")
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(_format verilog)
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(_widget wgt_my_ips_src
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(_input
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(_ip "ipcore/SPLL/SPLL.idf"
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(_timespec "2024-03-10T18:50:53")
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(_ip_source_item "ipcore/SPLL/SPLL.v"
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(_timespec "2024-03-10T18:50:53")
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(_widget wgt_import_logic_con_file
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(_file "app.fdc"
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(_format fdc)
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(_widget wgt_edit_user_cons
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(_attribute _click_to_run (_switch ON))
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(_widget wgt_simulation
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(_option compiled_lib_location (_string "pango_sim_libraries"))
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(_option verilog_options (_string ""))
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(_option gen_param (_string ""))
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(_option simulate_runtime (_string "10000ms"))
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(_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
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(_input
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(_file "source/test/test_transmitter.v"
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(_format verilog)
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(_timespec "2024-03-08T21:15:01")
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(_file "source/test/test_baud_rate_gen.v"
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(_format verilog)
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(_timespec "2024-03-08T21:15:01")
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(_format verilog)
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(_timespec "2024-03-08T21:15:01")
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(_file "source/test/test_uart_reg_reader.v"
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(_format verilog)
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(_timespec "2024-03-08T21:15:01")
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(_file "source/test/test_spi_reg_reader.v"
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(_format verilog)
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(_timespec "2024-03-10T18:52:01")
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(_file "source/test/test_timecode_decoder.v" + "test_timecode_decoder:"
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(_format verilog)
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(_timespec "2024-03-08T21:15:01")
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(_task tsk_compile
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(_command cmd_compile
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(_gci_state (_integer 2))
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(_db_output
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(_file "compile/Top_comp.adf"
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(_format adif)
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(_timespec "2024-08-06T09:44:18")
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(_file "compile/Top.cmr"
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(_timespec "2024-08-06T09:44:18")
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(_widget wgt_rtl_view
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(_attribute _click_to_run (_switch ON))
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(_task tsk_synthesis
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(_command cmd_synthesize
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(_gci_state (_integer 2))
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(_option ads (_switch ON))
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(_option selected_syn_tool_opt (_integer 2))
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(_db_output
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(_file "synthesize/Top_syn.adf"
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(_format adif)
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(_timespec "2024-08-06T09:44:31")
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(_output
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(_file "synthesize/Top_syn.vm"
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(_format structural_verilog)
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(_file "synthesize/Top.snr"
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(_format text)
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(_file "synthesize/snr.db"
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(_timespec "2024-08-06T09:44:33")
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(_widget wgt_tech_view
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(_attribute _click_to_run (_switch ON))
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(_widget wgt_map_constraint
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(_widget wgt_my_fic_src
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(_widget wgt_inserter_gui_view
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(_attribute _click_to_run (_switch ON))
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(_task tsk_devmap
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(_command cmd_devmap
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(_widget wgt_edit_placement_cons
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(_attribute _click_to_run (_switch ON))
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(_widget wgt_edit_route_cons
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(_attribute _click_to_run (_switch ON))
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(_task tsk_pnr
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(_command cmd_pnr
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(_gci_state (_integer 2))
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(_widget wgt_power_calculator
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(_attribute _click_to_run (_switch ON))
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(_widget wgt_timing_analysis
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(_attribute _click_to_run (_switch ON))
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(_command cmd_report_post_pnr_timing
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(_widget wgt_arch_browser
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(_attribute _click_to_run (_switch ON))
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(_command cmd_report_power
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(_gci_state (_integer 0))
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(_attribute _auto_exe_lock (_switch OFF))
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(_attribute _auto_exe (_switch OFF))
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(_command cmd_gen_netlist
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(_gci_state (_integer 0))
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(_attribute _auto_exe_lock (_switch OFF))
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(_attribute _auto_exe (_switch OFF))
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(_task tsk_gen_bitstream
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(_command cmd_gen_bitstream
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(_gci_state (_integer 2))
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(_output
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(_file "generate_bitstream/Top.sbit"
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(_timespec "2024-08-06T09:45:27")
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(_format text)
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