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46 lines
1.0 KiB
46 lines
1.0 KiB
module zutils_pluse_generator_v2 (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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input wire [31:0] pluse_width,
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input wire [31:0] pluse_delay,
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input wire trigger,
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output reg output_signal
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);
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reg [31:0] counter = 0;
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reg [31:0] tohigh_count = 0;
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reg [31:0] counter_init_count = 0;
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always @(*) begin
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tohigh_count <= pluse_width;
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counter_init_count <= pluse_width + pluse_delay;
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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counter <= 0;
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output_signal <= 0;
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end else begin
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if (trigger) begin
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counter <= counter_init_count;
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output_signal <= 0;
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end else begin
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if (counter != 0) begin
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counter <= counter - 1;
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if (counter == tohigh_count) begin
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output_signal <= 1;
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end
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end else begin
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output_signal <= 0;
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counter <= 0;
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end
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end
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end
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end
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endmodule
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