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80 lines
1.9 KiB
80 lines
1.9 KiB
module zutils_trigger_sig_gen (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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input start_sig,
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input stop_sig,
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input [31:0] cfg_freq_cnt,
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input [31:0] cfg_pluse_cnt,
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output reg output_signal
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);
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reg [31:0] cfg_freq_cnt_cache;
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reg [31:0] cfg_pluse_cnt_cache;
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reg work_state;
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reg [31:0] freq_cnt;
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reg [31:0] pluse_cnt;
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reg first_start;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cfg_freq_cnt_cache <= 0;
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cfg_pluse_cnt_cache <= 0;
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work_state <= 0;
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work_state <= 0;
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freq_cnt <= 0;
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pluse_cnt <= 0;
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output_signal <= 0;
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first_start <= 1;
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end else begin
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case (work_state)
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0: begin
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if (start_sig || first_start) begin
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work_state <= 1;
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cfg_freq_cnt_cache <= cfg_freq_cnt;
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cfg_pluse_cnt_cache <= cfg_pluse_cnt_cache;
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freq_cnt <= 0;
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pluse_cnt <= 0;
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output_signal <= 0;
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first_start <= 0;
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end else begin
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output_signal <= 0;
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end
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end
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1: begin
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if (!stop_sig) begin
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if (freq_cnt >= cfg_freq_cnt_cache) begin
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freq_cnt <= 0;
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output_signal <= 1;
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if (cfg_pluse_cnt_cache != 0) begin
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if (pluse_cnt == cfg_pluse_cnt_cache - 1) begin
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work_state <= 0;
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end else begin
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pluse_cnt <= pluse_cnt + 1;
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end
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end
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end else begin
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freq_cnt <= freq_cnt + 1;
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output_signal <= 0;
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end
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end else begin
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work_state <= 0;
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end
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end
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default: work_state <= 0;
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endcase
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end
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end
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endmodule
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