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module zutils_edge_detecter (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
input wire in_signal,
output reg in_signal_last,
output reg in_signal_rising_edge,
output reg in_signal_falling_edge,
output reg in_signal_edge
);
initial begin
in_signal_last = 0;
in_signal_rising_edge = 0;
in_signal_falling_edge = 0;
in_signal_edge = 0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
in_signal_last <= 0;
end else begin
in_signal_last <= in_signal;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
in_signal_rising_edge <= 0;
in_signal_falling_edge <= 0;
in_signal_edge <= 0;
end else begin
if (in_signal_last == 0 && in_signal == 1) begin
in_signal_rising_edge <= 1;
in_signal_falling_edge <= 0;
in_signal_edge <= 1;
end else if (in_signal_last == 1 && in_signal == 0) begin
in_signal_rising_edge <= 0;
in_signal_falling_edge <= 1;
in_signal_edge <= 1;
end else begin
in_signal_rising_edge <= 0;
in_signal_falling_edge <= 0;
in_signal_edge <= 0;
end
end
end
endmodule