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55 lines
2.0 KiB
55 lines
2.0 KiB
`include "config.v"
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/*
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* Hacky baud rate generator to divide a 50MHz clock into a 115200 baud
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* rx/tx pair where the rx clcken oversamples by 16x.
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*/
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module rd_data_router (
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input [31:0] addr,
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input [31:0] stm32_rd_data,
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input [31:0] fpga_test_rd_data,
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input [31:0] control_sensor_rd_data,
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input [31:0] ttlin1_rd_data,
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input [31:0] ttlin2_rd_data,
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input [31:0] ttlin3_rd_data,
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input [31:0] ttlin4_rd_data,
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input [31:0] timecode_in_rd_data,
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input [31:0] genlock_in_rd_data,
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input [31:0] ttlout1_rd_data,
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input [31:0] ttlout2_rd_data,
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input [31:0] ttlout3_rd_data,
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input [31:0] ttlout4_rd_data,
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input [31:0] timecode_out_rd_data,
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input [31:0] genlock_out_rd_data,
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input [31:0] stm32_if_rd_data,
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input [31:0] debuger_rd_data,
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output reg [31:0] rd_data_out
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);
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always @(*) begin
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case (addr >> 8)
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`REG_ADD_OFF_STM32 >> 8: rd_data_out = stm32_rd_data;
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`REG_ADD_OFF_FPGA_TEST >> 8: rd_data_out = fpga_test_rd_data;
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`REG_ADD_OFF_CONTROL_SENSOR >> 8: rd_data_out = control_sensor_rd_data;
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`REG_ADD_OFF_TTLIN1 >> 8: rd_data_out = ttlin1_rd_data;
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`REG_ADD_OFF_TTLIN2 >> 8: rd_data_out = ttlin2_rd_data;
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`REG_ADD_OFF_TTLIN3 >> 8: rd_data_out = ttlin3_rd_data;
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`REG_ADD_OFF_TTLIN4 >> 8: rd_data_out = ttlin4_rd_data;
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`REG_ADD_OFF_TIMECODE_IN >> 8: rd_data_out = timecode_in_rd_data;
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`REG_ADD_OFF_GENLOCK_IN >> 8: rd_data_out = genlock_in_rd_data;
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`REG_ADD_OFF_TTLOUT1 >> 8: rd_data_out = ttlout1_rd_data;
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`REG_ADD_OFF_TTLOUT2 >> 8: rd_data_out = ttlout2_rd_data;
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`REG_ADD_OFF_TTLOUT3 >> 8: rd_data_out = ttlout3_rd_data;
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`REG_ADD_OFF_TTLOUT4 >> 8: rd_data_out = ttlout4_rd_data;
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`REG_ADD_OFF_TIMECODE_OUT >> 8: rd_data_out = timecode_out_rd_data;
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`REG_ADD_OFF_GENLOCK_OUT >> 8: rd_data_out = genlock_out_rd_data;
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`REG_ADD_OFF_STM32_IF >> 8: rd_data_out = stm32_if_rd_data;
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`REG_ADD_OFF_DEBUGER >> 8: rd_data_out = debuger_rd_data;
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default: rd_data_out = 0;
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endcase
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end
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endmodule
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