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69 lines
1.8 KiB
69 lines
1.8 KiB
`include "../config.v"
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module genlock_input_module #(
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parameter REG_START_ADD = 0,
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parameter SYS_CLOCK_FREQ = 10000000
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) (
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input clk, //! 时钟输入
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input rst_n, //! 复位输入
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input [31:0] addr, //! 寄存器地址
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input [31:0] wr_data, //! 写入数据
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input wr_en, //! 写使能
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output wire [31:0] rd_data, //! 读出数据
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input genlock_in_hsync, //! genlock hsync
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input genlock_in_vsync, //! genlock vsync
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input genlock_in_fsync, //! genlock fsync
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output genlock_freq_signal, //! genlock freq signal
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output genlock_in_state_led
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);
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reg [31:0] r1_genlock_freq_detect_bias;
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wire [31:0] r2_genlock_freq;
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wire [31:0] reg_wr_index;
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zutils_register_advanced #(
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.REG_START_ADD(REG_START_ADD)
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) _register (
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.clk (clk),
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.rst_n (rst_n),
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.addr (addr),
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.wr_data (wr_data),
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.wr_en (wr_en),
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.rd_data (rd_data),
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.reg1 (r1_genlock_freq_detect_bias),
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.reg2 (r2_genlock_freq),
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.reg_wr_sig(reg_wr_sig),
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.reg_index (reg_wr_index)
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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r1_genlock_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT;
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end else begin
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if (reg_wr_sig) begin
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case (reg_wr_index)
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1: r1_genlock_freq_detect_bias <= wr_data;
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default: begin
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end
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endcase
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end
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end
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end
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zutils_freq_detector_v2 freq_detector1 (
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.clk (clk),
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.rst_n (rst_n),
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.freq_detect_bias(r1_genlock_freq_detect_bias),
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.pluse_input (genlock_in_vsync),
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.pluse_width_cnt (r2_genlock_freq)
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);
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assign genlock_freq_signal = genlock_in_vsync;
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assign genlock_in_state_led = 1;
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endmodule
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