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75 lines
1.7 KiB
75 lines
1.7 KiB
//
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// @功能:
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// 1. 滤波(add later)
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// 2. 频率探测
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// 3. 输出灯光控制
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//
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module zutils_freq_detector
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(
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input clk, //! 时钟输入
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input rst_n, //! 复位输入
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input pluse_input, //! 输入信号1
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//处理后的信号输出
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output reg [31:0]pluse_width_cnt //! 输出捕获到的脉冲宽度
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);
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reg in_signal_last;
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reg in_signal_rising_edge; //! 上升沿
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//!in_signal_last 捕获
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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in_signal_last <= 0;
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end
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else begin
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in_signal_last <= pluse_input;
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end
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end
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//!边沿捕获
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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in_signal_rising_edge <= 0;
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end
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else begin
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if (in_signal_last == 0 && pluse_input == 1) begin
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in_signal_rising_edge <= 1;
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end
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else if (in_signal_last == 1 && pluse_input == 0) begin
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in_signal_rising_edge <= 0;
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end
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else begin
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in_signal_rising_edge <= 0;
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end
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end
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end
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// 计数器
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reg [31:0] pluse_width_cnt_reg;
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//!脉冲宽度计数
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pluse_width_cnt_reg <= 0;
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pluse_width_cnt <= 32'hffff_ffff;
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end
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else begin
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if (in_signal_rising_edge) begin
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pluse_width_cnt <= pluse_width_cnt_reg;
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pluse_width_cnt_reg <= 0;
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end
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else begin
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pluse_width_cnt_reg <= pluse_width_cnt_reg + 1;
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if(pluse_width_cnt_reg >= 32'd11000000) begin //TODO:支持可配置
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pluse_width_cnt <= 32'hffff_ffff;
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pluse_width_cnt_reg <= 0;
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end
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end
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end
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end
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endmodule
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