syncbox16ch_fpga/source/src/zutils/zutils_debug_pwm_generator.v

module zutils_debug_pwm_generator #(
    parameter SYS_CLOCK_FREQ = 100000000
) (
    input      clk,
    input      rst_n,
    output wire pwm100hz,
    output wire pwm101hz,
    output wire pwm102hz,
    output wire pwm103hz,
    output wire pwm104hz,
    output wire pwm105hz,
    output wire pwm106hz,
    output wire pwm107hz,
    output wire pwm108hz,
    output wire pwm109hz,
    output wire pwm110hz,
    output wire pwm111hz,
    output wire pwm112hz,
    output wire pwm113hz,
    output wire pwm114hz,
    output wire pwm115hz
);

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(100 * 100)  //10.00HZ
  ) pwm0 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm100hz)
  );
  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(101 * 100)  //10.10HZ
  ) pwm1 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm101hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(102 * 100)  //10.20HZ
  ) pwm2 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm102hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(103 * 100)  //10.30HZ
  ) pwm3 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm103hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(104 * 100)  //10.40HZ
  ) pwm4 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm104hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(105 * 100)  //10.50HZ
  ) pwm5 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm105hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(106 * 100)  //10.60HZ
  ) pwm6 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm106hz)
  );
  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(107 * 100)  //10.70HZ
  ) pwm7 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm107hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(108 * 100)  //10.80HZ
  ) pwm8 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm108hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(109 * 100)  //10.90HZ
  ) pwm9 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm109hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(110 * 100)  //11.00HZ
  ) pwm10 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm110hz)
  );
  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(111 * 100)  //11.10HZ
  ) pwm11 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm111hz)
  );
  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(112 * 100)  //11.20HZ
  ) pwm12 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm112hz)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(113 * 100)  //11.30HZ
  ) pwm13 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm113hz)
  );
  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(114 * 100)  //11.40HZ
  ) pwm14 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm114hz)
  );
  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(115 * 100)  //11.50HZ
  ) pwm15 (
      .clk          (clk),
      .rst_n        (rst_n),
      .ctrl_sig     (1'd1),
      .output_signal(pwm115hz)
  );


endmodule