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76 lines
1.7 KiB
76 lines
1.7 KiB
module transmitter (
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input wire [7:0] din,
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input wire wr_en,
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input wire clk_50m,
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input wire clken,
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input wire rest_n,
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output reg tx,
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output wire tx_busy,
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output wire [1:0] t_state,
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output wire [2:0] t_bitpos,
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output wire t_worksignal
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);
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parameter STATE_IDLE = 2'b00;
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parameter STATE_START = 2'b01;
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parameter STATE_DATA = 2'b10;
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parameter STATE_STOP = 2'b11;
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initial begin
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tx = 1'b1;
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end
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reg [7:0] data = 8'h00;
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reg [2:0] bitpos = 3'h0;
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reg [1:0] state = STATE_IDLE;
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reg worksignal = 0;
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assign workflag = (state != STATE_IDLE);
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always @(posedge clken, posedge wr_en) begin
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if (wr_en) begin
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worksignal <= 1'b1;
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data <= din;
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end else begin
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if (!workflag) worksignal <= 1'b0;
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end
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end
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always @(posedge clken or negedge rest_n) begin
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if (!rest_n) begin
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state <= STATE_IDLE;
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end else begin
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case (state)
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STATE_IDLE: begin
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tx <= 1'b1;
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if (worksignal) begin
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state <= STATE_START;
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bitpos <= 0;
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end
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end
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STATE_START: begin
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tx <= 1'b0;
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state <= STATE_DATA;
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end
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STATE_DATA: begin
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if (bitpos == 3'h7) state <= STATE_STOP;
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else bitpos <= bitpos + 3'h1;
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tx <= data[bitpos];
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end
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STATE_STOP: begin
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tx <= 1'b1;
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state <= STATE_IDLE;
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end
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default begin
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tx <= 1'b1;
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state <= STATE_IDLE;
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end
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endcase
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end
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end
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assign tx_busy = (state != STATE_IDLE);
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assign t_state = state;
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assign t_bitpos = bitpos;
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assign t_worksignal = worksignal;
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endmodule
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