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22 lines
538 B
22 lines
538 B
module zutils_reset_sig_gen (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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output reg rst_n_out
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);
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reg [31:0] counter = 0;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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counter <= 0;
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rst_n_out <= 0;
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end else begin
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if (counter < 10) begin
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rst_n_out <= 0;
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counter <= counter + 1;
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end else if (counter == 10) begin
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counter <= counter;
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rst_n_out <= 1;
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end
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end
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end
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endmodule
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