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115 lines
2.6 KiB
115 lines
2.6 KiB
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module timecode_generator #(
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parameter SYS_CLOCK_FREQ = 10000000
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) (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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input [31:0] timecode_format,
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input timecode0_wen,
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input [31:0] timecode0,
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output [31:0] timecode0_export,
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input timecode1_wen,
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input [31:0] timecode1,
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output [31:0] timecode1_export,
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input en,
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output wire out_timecode_serial_data,
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output wire out_trigger_sig,
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output wire [31:0] out_timecode0,
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output wire [31:0] out_timecode1
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);
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//
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wire [7:0] out_frame_num;
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wire out_drop_frame;
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wire frame_trigger_sig;
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wire first_frame_sig;
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timecode_basesig_generator #(
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
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) basesig_generator (
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.clk(clk),
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.rst_n(rst_n),
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.timecode_format(timecode_format),
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.en(en),
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.out_timecode_trigger_sig(frame_trigger_sig), //帧时钟触发信号
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.out_first_frame_sig(first_frame_sig),
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.out_frame_num(out_frame_num),
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.out_drop_frame(out_drop_frame)
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);
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reg [63:0] timecode;
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wire [63:0] timecode_next;
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timecode_nextcode nextcode (
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.frame_mum(out_frame_num),
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.drop(out_drop_frame),
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.timecode(timecode),
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.timecode_next(timecode_next)
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);
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reg timecode_trigger_sig;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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timecode <= 0;
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timecode_trigger_sig <= 0;
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end else begin
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if (!en) begin
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if (timecode0_wen || timecode1_wen) begin
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if (timecode0_wen) begin
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timecode[31:0] <= timecode0;
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end
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if (timecode1_wen) begin
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timecode[63:32] <= timecode1;
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end
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end
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end else begin
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if (frame_trigger_sig) begin
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if (!first_frame_sig) begin
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timecode <= timecode_next;
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end
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timecode_trigger_sig <= 1;
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end else begin
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timecode_trigger_sig <= 0;
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end
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end
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end
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end
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assign timecode0_export = timecode[31:0];
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assign timecode1_export = timecode[63:32];
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wire [63:0] out_timecode;
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timecode_serialization #(
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
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) serialization (
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.clk(clk),
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.rst_n(rst_n),
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.timecode_format(timecode_format),
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.trigger_sig(timecode_trigger_sig),
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.timecode(timecode),
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.out_timecode_serial_data(out_timecode_serial_data),
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.out_trigger_sig(out_trigger_sig),
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.out_timecode(out_timecode)
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);
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// out_timecode0
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// out_timecode1
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assign out_timecode0 = out_timecode[31:0];
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assign out_timecode1 = out_timecode[63:32];
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endmodule
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