zfpga_basic_protocol/zaf_regs.hpp

#pragma once
#define REGADD__STM32_COMMON   (0x0010)
#define REGADD__STM32_BUSINESS (0x0020)
#define REGADD__FPGA_START     (0x0100)

typedef enum {
  /**
   * @brief
   *  REG 0(16)  �豸��Ϣ�����Ĵ���
   */
  kreg_software_version = 0,
  kreg_manufacturer0    = 1,
  kreg_manufacturer1    = 2,
  kreg_product_type_id  = 3,
  kreg_sn_id0           = 4,
  kreg_sn_id1           = 5,
  kreg_sn_id2           = 6,
  kreg_mac0             = 7,
  kreg_mac1             = 8,

  /**
   * @brief
   *  REG 16(32)  STM32���üĴ���0
   */
  kreg_stm32_obtaining_ip_mode = REGADD__STM32_COMMON + 0,
  kreg_stm32_ip                = REGADD__STM32_COMMON + 1,
  kreg_stm32_gw                = REGADD__STM32_COMMON + 2,
  kreg_stm32_netmask           = REGADD__STM32_COMMON + 3,
  kreg_stm32_config0           = REGADD__STM32_COMMON + 4,  // bit0: timecode report enable, bit1: camera sync report enable

  kreg_stm32_action0     = REGADD__STM32_COMMON + 14,  // action reg
  kreg_stm32_action_val0 = REGADD__STM32_COMMON + 15,  // action val reg

  kreg_stm32_temperature     = REGADD__STM32_BUSINESS + 0,
  kreg_stm32_fan0_error_flag = REGADD__STM32_BUSINESS + 1,

} RegAdd_t;