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#include "fpga_if.h"
/**
* @brief fpga_if��ʼ�� */ #define TAG "fpga_if"
static fpga_if_t fpga_if; zaf_gpio_t spi_cs; SemaphoreHandle_t m_spilock;
#define CHECK_PIN(pin0, pin1) \
{ \ zaf_gpio_write(&pin0, false); \ bool readbak = zaf_gpio_read(&pin1); \ if (readbak != false) { \ ZLOGI(TAG, "pin %s %s error", #pin0, #pin1); \ } \ osDelay(1); \ zaf_gpio_write(&pin0, true); \ readbak = zaf_gpio_read(&pin1); \ if (readbak != true) { \ ZLOGI(TAG, "pin %s %s error", #pin0, #pin1); \ } \ }
// void fpga_test() {
// while (true) {
// CHECK_PIN(fpga_if.fpga_reserve_iob0, fpga_if.fpga_reserve_ioa0);
// CHECK_PIN(fpga_if.fpga_reserve_iob1, fpga_if.fpga_reserve_ioa1);
// CHECK_PIN(fpga_if.fpga_reserve_iob2, fpga_if.fpga_reserve_ioa2);
// CHECK_PIN(fpga_if.fpga_reserve_iob3, fpga_if.fpga_reserve_ioa3);
// CHECK_PIN(fpga_if.fpga_reserve_iob4, fpga_if.fpga_reserve_ioa4);
// CHECK_PIN(fpga_if.fpga_reserve_iob5, fpga_if.fpga_reserve_ioa5);
// CHECK_PIN(fpga_if.fpga_reserve_iob6, fpga_if.fpga_reserve_ioa6);
// CHECK_PIN(fpga_if.fpga_reserve_iob7, fpga_if.fpga_reserve_ioa7);
// }
// }
void fpga_if_init() { //
uint8_t rxbuf[1]; m_spilock = xSemaphoreCreateRecursiveMutex(); /**
* @brief ����SPI��δ������һ֡����֮ǰ��ʱ�����ǵ͵�ƽ(������Ӧ��Ϊ��)������ * �ٴ���һ֡���ݣ�ʹʱ���߱�Ϊ�ߵ�ƽ�� */
fpga_if.spi1 = &hspi1; zaf_gpio_init_as_output(&spi_cs, SPI_CS, kxs_gpio_nopull, false, true); HAL_SPI_Receive(fpga_if.spi1, rxbuf, 1, 1000);
//! ioa0 ��ʱ���ڵ�����λ����
zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa0, FPGA_RESERVE_IOA0, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa1, FPGA_RESERVE_IOA1, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa2, FPGA_RESERVE_IOA2, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa3, FPGA_RESERVE_IOA3, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa4, FPGA_RESERVE_IOA4, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa5, FPGA_RESERVE_IOA5, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa6, FPGA_RESERVE_IOA6, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_input(&fpga_if.fpga_reserve_ioa7, FPGA_RESERVE_IOA7, kxs_gpio_nopull, kxs_gpio_no_irq, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob0, FPGA_RESERVE_IOB0, kxs_gpio_od, false, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob1, FPGA_RESERVE_IOB1, kxs_gpio_od, false, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob2, FPGA_RESERVE_IOB2, kxs_gpio_od, false, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob3, FPGA_RESERVE_IOB3, kxs_gpio_od, false, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob4, FPGA_RESERVE_IOB4, kxs_gpio_od, false, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob5, FPGA_RESERVE_IOB5, kxs_gpio_od, false, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob6, FPGA_RESERVE_IOB6, kxs_gpio_od, false, false); zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob7, FPGA_RESERVE_IOB7, kxs_gpio_od, false, false);
#if 1
zaf_gpio_write(&fpga_if.fpga_reserve_iob0, false); osDelay(2); // �ȴ�FPGA��Դ�ȶ�
zaf_gpio_write(&fpga_if.fpga_reserve_iob0, true); osDelay(2); // �ȴ�FPGA�ڲ�ʱ���ȶ�
#endif
while (true) { uint32_t rxbuf; fpga_if_spi_read_data(0x1000, &rxbuf); if (rxbuf == 0x1000) { break; } ZLOGI(TAG, "waitting for fpga is ready %x",rxbuf); osDelay(10); } }
/**
* @brief SPI�Ĵ���дָ�� * * @param add * @param txdata * @param rxdata */ static void _fpga_if_spi_write_data(SPI_HandleTypeDef *hspi, uint32_t add, uint32_t txdata, uint32_t *rxdata) { uint8_t txbuf[2 + 5] = {0}; uint8_t rxbuf[2 + 5] = {0}; txbuf[0] = add & 0xFF; txbuf[1] = (add >> 8) & 0xFF; txbuf[1] |= 0x80; // write flag
txbuf[2] = txdata & 0xFF; txbuf[3] = (txdata >> 8) & 0xFF; txbuf[4] = (txdata >> 16) & 0xFF; txbuf[5] = (txdata >> 24) & 0xFF;
HAL_SPI_TransmitReceive_DMA(hspi, txbuf, rxbuf, 2 + 5); while (HAL_SPI_GetState(hspi) != HAL_SPI_STATE_READY) { }
// HAL_SPI_Transmit(hspi, txbuf, 2 + 4, 1000);
if (rxdata) { *rxdata = rxbuf[2] | (rxbuf[3] << 8) | (rxbuf[4] << 16) | (rxbuf[5] << 24); } } /**
* @brief SPI�Ĵ�����ָ�� * * @param add * @param rxdata */ static void _fpga_if_spi_read_data(SPI_HandleTypeDef *hspi, uint32_t add, uint32_t *rxdata) { uint8_t txbuf[2 + 5] = {0}; uint8_t rxbuf[2 + 5] = {0};
txbuf[0] = add & 0xFF; txbuf[1] = (add >> 8) & 0xFF; txbuf[2] = 0; txbuf[3] = 0; txbuf[4] = 0; txbuf[5] = 0; HAL_SPI_TransmitReceive_DMA(hspi, txbuf, rxbuf, 2 + 5); while (HAL_SPI_GetState(hspi) != HAL_SPI_STATE_READY) { } if (rxdata) { *rxdata = rxbuf[2] | (rxbuf[3] << 8) | (rxbuf[4] << 16) | (rxbuf[5] << 24); } }
void fpga_if_spi_write_data(uint32_t add, uint32_t txdata, uint32_t *rxdata) { xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY); zaf_gpio_write(&spi_cs, false); _fpga_if_spi_write_data(fpga_if.spi1, add, txdata, rxdata); zaf_gpio_write(&spi_cs, true); zaf_delay_us(1); zaf_gpio_write(&spi_cs, false); _fpga_if_spi_read_data(fpga_if.spi1, add, rxdata); zaf_gpio_write(&spi_cs, true); xSemaphoreGiveRecursive(m_spilock); } void fpga_if_spi_read_data(uint32_t add, uint32_t *rxdata) { xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY); zaf_gpio_write(&spi_cs, false); _fpga_if_spi_read_data(fpga_if.spi1, add, rxdata); zaf_gpio_write(&spi_cs, true); xSemaphoreGiveRecursive(m_spilock); }
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