fpga_led_test/led_test.pds

(_flow fab_demo "2021.1-SP7"
    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Jan 12 18:53:10 2024")
    (_version "1.0.5")
    (_status "initial")
    (_project 
    )
    (_task tsk_setup
        (_widget wgt_select_arch
            (_input
                (_part
                    (_family Logos)
                    (_device PGL22G)
                    (_speedgrade -6)
                    (_package MBG324)
                )
            )
        )
        (_widget wgt_my_design_src
            (_input
                (_file "source/src/top.v" + "Top:"
                    (_format verilog)
                    (_timespec "2024-01-12T18:48:50")
                )
                (_file "source/src/spi_reg_reader.v"
                    (_format verilog)
                    (_timespec "2024-01-11T09:43:30")
                )
                (_file "source/src/zutils/zutils_pluse_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-11T16:29:59")
                )
                (_file "source/src/zutils/zutils_edge_detecter.v"
                    (_format verilog)
                    (_timespec "2024-01-08T22:12:54")
                )
                (_file "source/src/zutils/zutils_register.v"
                    (_format verilog)
                    (_timespec "2024-01-11T15:21:44")
                )
                (_file "source/src/zutils/zutils_multiplexer_4t1.v"
                    (_format verilog)
                    (_timespec "2024-01-09T10:15:13")
                )
                (_file "source/src/zutils/zutils_debug_led.v"
                    (_format verilog)
                    (_timespec "2024-01-08T16:55:37")
                )
                (_file "source/src/zutils/zutils_signal_filter.v"
                    (_format verilog)
                    (_timespec "2024-01-08T22:15:39")
                )
                (_file "source/src/zutils/zutils_clk_parser.v"
                    (_format verilog)
                    (_timespec "2024-01-08T16:55:21")
                )
                (_file "source/src/zutils/zutils_multiplexer_16t1.v"
                    (_format verilog)
                    (_timespec "2024-01-09T10:30:12")
                )
                (_file "source/src/output/ttl_output.v"
                    (_format verilog)
                    (_timespec "2024-01-10T22:09:45")
                )
                (_file "source/src/zutils/zutils_pwm_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-10T20:45:33")
                )
                (_file "source/src/rd_data_router.v"
                    (_format verilog)
                    (_timespec "2024-01-11T20:38:49")
                )
                (_file "source/src/zutils/zutils_reset_sig_gen.v"
                    (_format verilog)
                    (_timespec "2024-01-08T22:22:50")
                )
                (_file "source/src/zutils/zutils_multiplexer_2t1.v"
                    (_format verilog)
                    (_timespec "2024-01-09T10:38:01")
                )
                (_file "source/src/zutils/zutils_multiplexer_32t1.v"
                    (_format verilog)
                    (_timespec "2024-01-09T10:30:11")
                )
                (_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
                    (_format verilog)
                    (_timespec "2024-01-10T20:51:41")
                )
                (_file "source/src/xsync_internal_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-12T17:30:41")
                )
                (_file "source/src/zutils/zutils_pwm_generator_advanced.v"
                    (_format verilog)
                    (_timespec "2024-01-10T20:50:52")
                )
                (_file "source/src/zutils/zutils_register_advanced.v"
                    (_format verilog)
                    (_timespec "2024-01-11T15:21:48")
                )
                (_file "source/src/zutils/zutils_genlock_clk_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-10T21:10:08")
                )
                (_file "source/src/zutils/zutils_multiplexer_32t1_v2.v"
                    (_format verilog)
                    (_timespec "2024-01-09T20:13:29")
                )
                (_file "source/src/zutils/ztutils_timecode_next_code.v"
                    (_format verilog)
                    (_timespec "2024-01-09T21:34:17")
                )
                (_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-10T20:51:41")
                )
                (_file "source/src/xsync_internal_sub/internal_timecode_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-10T20:51:41")
                )
                (_file "source/src/timecode/timecode_nextcode.v"
                    (_format verilog)
                    (_timespec "2024-01-10T19:49:22")
                )
                (_file "source/src/timecode/timecode_basesig_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-10T20:52:39")
                )
                (_file "source/src/timecode/timecode_serialization.v"
                    (_format verilog)
                    (_timespec "2024-01-11T16:07:11")
                )
                (_file "source/src/timecode/timecode_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-11T15:07:28")
                )
                (_file "source/src/timecode_output.v"
                    (_format verilog)
                    (_timespec "2024-01-11T18:42:04")
                )
                (_file "source/src/camera_sync_signal_output.v"
                    (_format verilog)
                    (_timespec "2024-01-11T20:33:06")
                )
                (_file "source/src/timecode/timecode_decoder.v"
                    (_format verilog)
                    (_timespec "2024-01-12T11:59:27")
                )
                (_file "source/src/timecode/timecode_sample_sig_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-12T10:15:22")
                )
                (_file "source/src/timecode_input.v"
                    (_format verilog)
                    (_timespec "2024-01-12T13:46:21")
                )
                (_file "source/src/zutils/ztuils_sig_devide.v"
                    (_format verilog)
                    (_timespec "2024-01-12T14:14:11")
                )
                (_file "source/src/ttl_input.v"
                    (_format verilog)
                    (_timespec "2024-01-12T16:27:36")
                )
                (_file "source/src/zutils/zutils_signal_filter_advance.v"
                    (_format verilog)
                    (_timespec "2024-01-12T14:02:02")
                )
                (_file "source/src/timecode/timecode_comparator.v"
                    (_format verilog)
                    (_timespec "2024-01-12T17:32:04")
                )
            )
        )
        (_widget wgt_my_ips_src
            (_input
                (_ip "ipcore/SPLL/SPLL.idf"
                    (_timespec "2024-01-11T09:39:18")
                    (_ip_source_item "ipcore/SPLL/SPLL.v"
                        (_timespec "2024-01-11T09:39:18")
                    )
                )
                (_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf"
                    (_timespec "2024-01-09T18:49:35")
                )
            )
        )
        (_widget wgt_import_logic_con_file
            (_input
                (_file "led_test.fdc"
                    (_format fdc)
                    (_timespec "2024-01-12T18:41:11")
                )
            )
        )
        (_widget wgt_edit_user_cons
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_simulation
            (_option compiled_lib_location (_string "pango_sim_libraries"))
            (_option verilog_options (_string ""))
            (_option gen_param (_string ""))
            (_option simulate_runtime (_string "10000ms"))
            (_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
            (_input
                (_file "source/test/test_transmitter.v"
                    (_format verilog)
                    (_timespec "2023-12-13T19:33:40")
                )
                (_file "source/test/test_baud_rate_gen.v"
                    (_format verilog)
                    (_timespec "2023-12-13T19:30:23")
                )
                (_file "source/test/test_top.v"
                    (_format verilog)
                    (_timespec "2024-01-11T16:00:43")
                )
                (_file "source/test/test_uart_reg_reader.v"
                    (_format verilog)
                    (_timespec "2023-12-15T22:18:26")
                )
                (_file "source/test/test_spi_reg_reader.v"
                    (_format verilog)
                    (_timespec "2023-12-15T22:10:16")
                )
                (_file "source/test/test_timecode_generator.v"
                    (_format verilog)
                    (_timespec "2024-01-10T21:54:42")
                )
                (_file "source/test/test_timecode_decoder.v" + "test_timecode_decoder:"
                    (_format verilog)
                    (_timespec "2024-01-12T13:15:41")
                )
            )
        )
    )
    (_task tsk_compile
        (_command cmd_compile
            (_gci_state (_integer 2))
            (_db_output
                (_file "compile/Top_comp.adf"
                    (_format adif)
                    (_timespec "2024-01-12T18:49:03")
                )
            )
            (_output
                (_file "compile/Top.cmr"
                    (_format verilog)
                    (_timespec "2024-01-12T18:49:02")
                )
                (_file "compile/cmr.db"
                    (_format text)
                    (_timespec "2024-01-12T18:49:04")
                )
            )
        )
        (_widget wgt_rtl_view
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_synthesis
        (_command cmd_synthesize
            (_gci_state (_integer 2))
            (_option ads (_switch ON))
            (_option selected_syn_tool_opt (_integer 2))
            (_db_output
                (_file "synthesize/Top_syn.adf"
                    (_format adif)
                    (_timespec "2024-01-12T18:50:26")
                )
            )
            (_output
                (_file "synthesize/Top_syn.vm"
                    (_format structural_verilog)
                    (_timespec "2024-01-12T18:50:31")
                )
                (_file "synthesize/Top.snr"
                    (_format text)
                    (_timespec "2024-01-12T18:50:35")
                )
                (_file "synthesize/snr.db"
                    (_format text)
                    (_timespec "2024-01-12T18:50:35")
                )
            )
        )
        (_widget wgt_tech_view
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_map_constraint
        )
        (_widget wgt_my_fic_src
        )
        (_widget wgt_inserter_gui_view
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_devmap
        (_command cmd_devmap
            (_gci_state (_integer 2))
            (_db_output
                (_file "device_map/Top_map.adf"
                    (_format adif)
                    (_timespec "2024-01-12T18:50:42")
                )
            )
            (_output
                (_file "device_map/Top_dmr.prt"
                    (_format text)
                    (_timespec "2024-01-12T18:50:41")
                )
                (_file "device_map/Top.dmr"
                    (_format text)
                    (_timespec "2024-01-12T18:50:42")
                )
                (_file "device_map/dmr.db"
                    (_format text)
                    (_timespec "2024-01-12T18:50:42")
                )
            )
        )
        (_widget wgt_edit_placement_cons
            (_attribute _click_to_run (_switch ON))
            (_input
                (_file "device_map/led_test.pcf"
                    (_format pcf)
                    (_timespec "2024-01-12T18:50:42")
                )
            )
        )
        (_widget wgt_edit_route_cons
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_pnr
        (_command cmd_pnr
            (_gci_state (_integer 2))
            (_option mode (_string "fast"))
            (_db_output
                (_file "place_route/Top_pnr.adf"
                    (_format adif)
                    (_timespec "2024-01-12T18:52:22")
                )
            )
            (_output
                (_file "place_route/Top.prr"
                    (_format text)
                    (_timespec "2024-01-12T18:52:22")
                )
                (_file "place_route/Top_prr.prt"
                    (_format text)
                    (_timespec "2024-01-12T18:52:21")
                )
                (_file "place_route/clock_utilization.txt"
                    (_format text)
                    (_timespec "2024-01-12T18:52:21")
                )
                (_file "place_route/Top_plc.adf"
                    (_format adif)
                    (_timespec "2024-01-12T18:50:52")
                )
                (_file "place_route/Top_pnr.netlist"
                    (_format text)
                    (_timespec "2024-01-12T18:52:22")
                )
                (_file "place_route/prr.db"
                    (_format text)
                    (_timespec "2024-01-12T18:52:23")
                )
            )
        )
        (_widget wgt_power_calculator
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_timing_analysis
            (_attribute _click_to_run (_switch ON))
        )
        (_command cmd_report_post_pnr_timing
            (_gci_state (_integer 2))
            (_attribute _auto_exe_lock (_switch OFF))
            (_db_output
                (_file "report_timing/Top_rtp.adf"
                    (_format adif)
                    (_timespec "2024-01-12T18:52:30")
                )
            )
            (_output
                (_file "report_timing/Top.rtr"
                    (_format text)
                    (_timespec "2024-01-12T18:52:30")
                )
                (_file "report_timing/rtr.db"
                    (_format text)
                    (_timespec "2024-01-12T18:52:31")
                )
            )
        )
        (_widget wgt_arch_browser
            (_attribute _click_to_run (_switch ON))
        )
        (_command cmd_report_power
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
            (_attribute _auto_exe (_switch OFF))
        )
        (_command cmd_gen_netlist
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
            (_attribute _auto_exe (_switch OFF))
        )
    )
    (_task tsk_gen_bitstream
        (_command cmd_gen_bitstream
            (_gci_state (_integer 2))
            (_output
                (_file "generate_bitstream/Top.sbit"
                    (_format text)
                    (_timespec "2024-01-12T18:53:08")
                )
                (_file "generate_bitstream/Top.smsk"
                    (_format text)
                    (_timespec "2024-01-12T18:53:08")
                )
                (_file "generate_bitstream/Top.bgr"
                    (_format text)
                    (_timespec "2024-01-12T18:53:08")
                )
                (_file "generate_bitstream/bgr.db"
                    (_format text)
                    (_timespec "2024-01-12T18:53:09")
                )
            )
        )
    )
)