fpga_led_test/source/test/test_timecode_decoder.v

`timescale 10ns / 10ns
module test_timecode_decoder;
  reg sys_clk;
  reg rst_n;

  reg timecode_in;

  reg one_timecode_end;
  reg datanow;

  wire timecode_in_state;
  wire timecode_tigger_sig;
  wire [63:0] timecode_data;
  wire timecode_serial_data;
  reg [7:0] offset;

  timecode_decoder #(
      .SYS_CLOCK_FREQ(10000000)
  ) timecode_decoder_inst (
      .clk  (sys_clk),
      .rst_n(rst_n),

      .timecode_in(timecode_in),
      .timecode_in_state(timecode_in_state),

      .timecode_tigger_sig(timecode_tigger_sig),
      .timecode_data(timecode_data),
      .timecode_serial_data(timecode_serial_data)
  );


  // 250us
  task timecode_generator;
    input [79:0] data;
    integer i;
    begin
      for (i = 0; i < 80; i = i + 1) begin
        offset = i;
        if (data[i]) begin
          datanow = 1;
        end else begin
          datanow = 0;
        end
        timecode_in = ~timecode_in;
        #25000;
        if (data[i]) begin
          timecode_in = ~timecode_in;
        end
        #25000;
      end
    end
  endtask

  initial begin
    sys_clk = 0;
    rst_n   = 0;
    #100;
    rst_n = 1;
    timecode_in = 0;
    one_timecode_end = 0;
    #100;

    // 
    // timecode_generator(79'h1234_4321_1234_4321_CFFB);
    // timecode_generator(79'h0000_0000_0000_0000_CFFB);
    timecode_generator(80'hBFFC_0000_0000_0000_0000);
    // timecode_generator(79'b1011_1111_1111_1100_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000);
    //FFFF
    //4444
    //16+16+16+16+16
    //  32    32  80
    //

    // timecode_generator(79'hBFFC_0000_0000_0000_0000);
    // timecode_generator(79'hBFFC_0000_0000_0000_0000);
    one_timecode_end = 1;
    #1000000;
    timecode_generator(80'hBFFC_0102_0304_0506_0102);

    #100000000;
    $stop;
  end
  always #5 sys_clk = ~sys_clk;  // 50MHZ时钟
endmodule