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IP Generator (Version 2021.1-SP7 build 86875)Check out license ...Start generating at 2024-01-07 14:18Instance: DebugCoreIst (D:\workspace\fpga_demo\led_test\ipcore\DebugCoreIst\DebugCoreIst.idf)IP: DebugCore (1.3)Part: Logos-PGL22G-MBG324--6Create directory 'rtl' ...Copy 'rtl\ips_dbc_cfg_reg_file_v1_0.v' to 'rtl' ...Copy 'rtl\ips_dbc_compare_256b_v1_0.v' to 'rtl' ...Copy 'rtl\ips_dbc_data_capture_mem_v1_0.v' to 'rtl' ...Copy 'rtl\ips_dbc_debug_core_v1_3.v' to 'rtl' ...Copy 'rtl\ips_dbc_hub_decode_v1_2.v' to 'rtl' ...Copy 'rtl\ips_dbc_rd_addr_gen_v1_3.v' to 'rtl' ...Copy 'rtl\ips_dbc_storage_condition_v1_3.v' to 'rtl' ...Copy 'rtl\ips_dbc_storage_qualification_v1_2.v' to 'rtl' ...Copy 'rtl\ips_dbc_trig_unit_v1_3.v' to 'rtl' ...Copy 'rtl\ips_dbc_trigger_condition_v1_3.v' to 'rtl' ...Copy 'rtl\ips_dbc_trigger_output_v1_2.v' to 'rtl' ...Copy 'ips_dbc_wrapper_v1_3.v.xml' ...Copy 'ips_dbc_inst.fdc.xml' ...Compile file 'ips_dbc_wrapper_v1_3.v.xml' to 'DebugCoreIst.v' ...Found top module 'DebugCoreIst' in file 'DebugCoreIst.v'.Compile file 'ips_dbc_inst.fdc.xml' to 'DebugCoreIst.fdc' ...Create template file 'DebugCoreIst_tmpl.v' ...Create template file 'DebugCoreIst_tmpl.vhdl' ...There are 12 source files to synthesize.Synthesis is disabled.Done: 0 error(s), 0 warning(s)
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