fpga_led_test/source/src/monitor_line.v

/*
 * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud
 * rx/tx pair where the rx clcken oversamples by 16x.
 */
module monitor_line (
    input  wire clk_50m,
    input  wire rst_n,
    input  wire in,
    output reg out
);


  always @(posedge clk_50m or negedge rst_n) begin
    if (!rst_n) out <= 1'b0;
    else out <= in;
  end

endmodule