fpga_led_test/source/test/test_uart_reg_reader.v

`timescale 1ns / 1ns
module test_uart_reg_reader;
  // Inputs
  reg clk_50m;
  reg rst_n;

  reg [31:0] reg_data;
  wire [31:0] reg_add;
  wire reg_add_valid;
  reg uart_rx_pin;
  wire uart_tx_pin;

  uart_reg_reader uart_reg_reader_impl (
      .clk(clk_50m),
      .rst_n(rst_n),
      .reg_data(reg_data),
      .reg_add(reg_add),
      .reg_add_valid(reg_add_valid),
      .uart_rx_pin(uart_rx_pin),
      .uart_tx_pin(uart_tx_pin)
  );


  initial begin
    // Initialize Inputs
    clk_50m = 0;
    rst_n = 0;
    reg_data = 31'h11223344;
    uart_rx_pin = 1;

    #10;
    rst_n = 1;

    #1000;
    uart_rx_pin = 1;

    #(8.680 * 1000);
    uart_rx_pin = 0;
    #(8.680 * 1000);
    uart_rx_pin = 1;
    #(8.680 * 1000);
    uart_rx_pin = 0;
    #(8.680 * 1000);
    uart_rx_pin = 1;
    #(8.680 * 1000);
    uart_rx_pin = 0;
    #(8.680 * 1000);
    uart_rx_pin = 1;
    #(8.680 * 1000);
    uart_rx_pin = 0;
    #(8.680 * 1000);
    uart_rx_pin = 1;
    #(8.680 * 1000);
    uart_rx_pin = 0;
    #(8.680 * 1000);
    uart_rx_pin = 1;
    #(8.680 * 1000);
    uart_rx_pin = 0;
    #(8.680 * 1000);
    uart_rx_pin = 1;

    #(100 * 8.680 * 1000);
    $stop;
  end
  always #10 clk_50m = ~clk_50m;  //20ns 50MHZ
endmodule