fpga_led_test/source/test/test_timecode_generator.v

`timescale 10ns / 10ns
module test_timecode_generator;
// module timecode_generator #(
//     parameter SYS_CLOCK_FREQ = 10000000
// ) (
//     input clk,   //clock input
//     input rst_n, //asynchronous reset input, low active

//     input [31:0] timecode_format,

//     input timecode0_wen,
//     input [31:0] timecode0,
//     input timecode1_wen,
//     input [31:0] timecode1,

//     input en,

//     output wire out_timecode_serial_data,
//     output wire out_trigger_sig,
//     output wire [31:0] out_timecode0,
//     output wire [31:0] out_timecode1
// )

    reg sys_clk;
    reg rst_n;

    reg [31:0] timecode_format;

    reg timecode0_wen;
    reg [31:0] timecode0;
    reg timecode1_wen;
    reg [31:0] timecode1;

    reg en;

    wire out_timecode_serial_data;
    wire out_trigger_sig;
    wire [31:0] out_timecode0;
    wire [31:0] out_timecode1;

    timecode_generator #(
        .SYS_CLOCK_FREQ(10000000)
    ) timecode_generator_inst (
        .clk(sys_clk),
        .rst_n(rst_n),

        .timecode_format(timecode_format),

        .timecode0_wen(timecode0_wen),
        .timecode0(timecode0),
        .timecode1_wen(timecode1_wen),
        .timecode1(timecode1),

        .en(en),

        .out_timecode_serial_data(out_timecode_serial_data),
        .out_trigger_sig(out_trigger_sig),
        .out_timecode0(out_timecode0),
        .out_timecode1(out_timecode1)
    );


  localparam FPS2398Format = 0;
  localparam FPS2400Format = 1;
  localparam FPS2500Format = 2;
  localparam FPS2997Format = 3;
  localparam FPS2997DropFormat = 4;
  localparam FPS3000Format = 5;

  initial begin
    sys_clk = 0;
    rst_n   = 0;
    en = 0;
    timecode0_wen = 0;
    timecode1_wen = 0;
    timecode0 = 0;
    timecode1 = 0;
    timecode_format = FPS2398Format;

    #100;
    rst_n = 1;

    #100;
    en = 1;

    #100000000;
    $stop;
  end
  always #5 sys_clk = ~sys_clk;  // 50MHZ时钟
endmodule