fpga_led_test/source/src/zutils/zutils_register.v

module zutils_register #(
    parameter REG_START_ADD = 0,
    parameter ADD_NUM       = 10
) (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    //regbus interface
    output reg [31:0] addr,
    input      [31:0] wr_data,
    input             wr_en,

    inout wire [31:0] rd_data  //received serial data 
);

  parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1;  //寄存器结束地址
  reg [31:0] data[REG_START_ADD:REG_END_ADD];
  integer i;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      for (i = 0; i < ADD_NUM; i = i + 1) begin
        data[i] <= 0;
      end
    end else begin
      if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) data[addr] <= wr_data;
    end
  end
  assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr] : 31'bz;


endmodule