fpga_led_test/source/test/test_top.v

`timescale 1ns / 1ns
module test_top;
  // Inputs
  reg clk_50m;
  reg rst_n;

  wire rxclk_en;
  wire txclk_en;

  wire [3:0] led;
  wire test_io3;
  wire test_io4;
  wire test_io5;
  wire test_io6;
  wire test_io7;
  wire test_io8;
  wire test_io9;
  wire test_io10;
  wire test_io11;

  Top top_impl (
      .sys_clk(clk_50m),
      .rst_n(rst_n),
      .led(led),
      .test_io3(test_io3),
      .test_io4(test_io4),
      .test_io5(test_io5),
      .test_io6(test_io6),
      .test_io7(test_io7),
      .test_io8(test_io8),
      .test_io9(test_io9),
      .test_io10(test_io10),
      .test_io11(test_io11)
  );

  initial begin
    // Initialize Inputs
    clk_50m = 0;
    rst_n   = 0;

    #100;
    rst_n = 1;

    #15;

    #300000;
    $stop;
  end
  always #10 clk_50m = ~clk_50m;  //20ns 50MHZ
endmodule