diff --git a/.gitignore b/.gitignore
index 16ca7ee..8011c58 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,3 +15,4 @@ device_map/bak/
 device_map/
 report_timing/
 ipcore/ram/ram.idf
+impl.tcl
diff --git a/impl.tcl b/impl.tcl
deleted file mode 100644
index 9e654f4..0000000
--- a/impl.tcl
+++ /dev/null
@@ -1,58 +0,0 @@
-#Generated by Fabric Compiler ( version 2021.1-SP7 <build 86875> ) at Fri Dec  8 16:54:29 2023
-
-add_design "D:/workspace/fpga_demo/led_test/source/led_test.v"
-set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
-compile -top_module led_test
-add_constraint "D:/workspace/fpga_demo/led_test/led_test.fdc"
-synthesize -ads -selected_syn_tool_opt 2 
-dev_map 
-pnr 
-pnr 
-pnr 
-pnr 
-pnr 
-pnr 
-synthesize -ads -selected_syn_tool_opt 2 
-dev_map 
-pnr 
-report_timing 
-gen_bit_stream 
-synthesize -ads -selected_syn_tool_opt 2 
-dev_map 
-pnr 
-report_timing 
-gen_bit_stream 
-add_design D:/workspace/fpga_demo/led_test/ipcore/clk_wiz_0/clk_wiz_0.idf
-add_design D:/workspace/fpga_demo/led_test/ipcore/ram/ram.idf
-remove_design -force D:/workspace/fpga_demo/led_test/ipcore/clk_wiz_0/clk_wiz_0.idf
-gen_bit_stream 
-gen_bit_stream 
-gen_bit_stream 
-gen_bit_stream 
-set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
-compile -top_module led_test
-synthesize -ads -selected_syn_tool_opt 2 
-dev_map 
-pnr 
-report_timing 
-gen_bit_stream 
-set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
-compile -top_module led_test
-synthesize -ads -selected_syn_tool_opt 2 
-dev_map 
-pnr 
-report_timing 
-gen_bit_stream 
-set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
-compile -top_module led_test
-set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
-compile -top_module led_test
-synthesize -ads -selected_syn_tool_opt 2 
-dev_map 
-pnr 
-report_timing 
-gen_bit_stream 
-add_simulation "D:/workspace/fpga_demo/led_test/source/vtf_led.test.v"
-remove_simulation -force "D:/workspace/fpga_demo/led_test/source/vtf_led.test.v"
-add_simulation "D:/workspace/fpga_demo/led_test/source/test.v"
-add_design "D:/workspace/fpga_demo/led_test/source/source/async.v"
diff --git a/led_test.pds b/led_test.pds
index df26307..ce82105 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Wed Dec 13 10:46:05 2023")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Wed Dec 13 10:56:09 2023")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -21,7 +21,7 @@
                     (_format verilog)
                     (_timespec "2023-12-12T18:38:54")
                 )
-                (_file "source/source/async.v"
+                (_file "source/async.v"
                     (_format verilog)
                     (_timespec "2023-12-13T10:42:04")
                 )
@@ -51,21 +51,21 @@
     )
     (_task tsk_compile
         (_command cmd_compile
-            (_gci_state (_integer 3))
+            (_gci_state (_integer 2))
             (_db_output
                 (_file "compile/led_test_comp.adf"
                     (_format adif)
-                    (_timespec "2023-12-12T18:39:06")
+                    (_timespec "2023-12-13T10:55:49")
                 )
             )
             (_output
                 (_file "compile/led_test.cmr"
                     (_format verilog)
-                    (_timespec "2023-12-12T18:39:06")
+                    (_timespec "2023-12-13T10:55:49")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:06")
+                    (_timespec "2023-12-13T10:55:49")
                 )
             )
         )
@@ -75,27 +75,27 @@
     )
     (_task tsk_synthesis
         (_command cmd_synthesize
-            (_gci_state (_integer 3))
+            (_gci_state (_integer 2))
             (_option ads (_switch ON))
             (_option selected_syn_tool_opt (_integer 2))
             (_db_output
                 (_file "synthesize/led_test_syn.adf"
                     (_format adif)
-                    (_timespec "2023-12-12T18:39:08")
+                    (_timespec "2023-12-13T10:55:53")
                 )
             )
             (_output
                 (_file "synthesize/led_test_syn.vm"
                     (_format structural_verilog)
-                    (_timespec "2023-12-12T18:39:08")
+                    (_timespec "2023-12-13T10:55:53")
                 )
                 (_file "synthesize/led_test.snr"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:08")
+                    (_timespec "2023-12-13T10:55:53")
                 )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:09")
+                    (_timespec "2023-12-13T10:55:53")
                 )
             )
         )
@@ -112,25 +112,25 @@
     )
     (_task tsk_devmap
         (_command cmd_devmap
-            (_gci_state (_integer 3))
+            (_gci_state (_integer 2))
             (_db_output
                 (_file "device_map/led_test_map.adf"
                     (_format adif)
-                    (_timespec "2023-12-12T18:39:11")
+                    (_timespec "2023-12-13T10:55:57")
                 )
             )
             (_output
                 (_file "device_map/led_test_dmr.prt"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:11")
+                    (_timespec "2023-12-13T10:55:57")
                 )
                 (_file "device_map/led_test.dmr"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:11")
+                    (_timespec "2023-12-13T10:55:57")
                 )
                 (_file "device_map/dmr.db"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:11")
+                    (_timespec "2023-12-13T10:55:57")
                 )
             )
         )
@@ -139,7 +139,7 @@
             (_input
                 (_file "device_map/led_test.pcf"
                     (_format pcf)
-                    (_timespec "2023-12-12T18:39:11")
+                    (_timespec "2023-12-13T10:55:57")
                 )
             )
         )
@@ -149,37 +149,37 @@
     )
     (_task tsk_pnr
         (_command cmd_pnr
-            (_gci_state (_integer 3))
+            (_gci_state (_integer 2))
             (_db_output
                 (_file "place_route/led_test_pnr.adf"
                     (_format adif)
-                    (_timespec "2023-12-12T18:39:16")
+                    (_timespec "2023-12-13T10:56:02")
                 )
             )
             (_output
                 (_file "place_route/led_test.prr"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:16")
+                    (_timespec "2023-12-13T10:56:02")
                 )
                 (_file "place_route/led_test_prr.prt"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:16")
+                    (_timespec "2023-12-13T10:56:02")
                 )
                 (_file "place_route/clock_utilization.txt"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:16")
+                    (_timespec "2023-12-13T10:56:02")
                 )
                 (_file "place_route/led_test_plc.adf"
                     (_format adif)
-                    (_timespec "2023-12-12T18:39:15")
+                    (_timespec "2023-12-13T10:56:01")
                 )
                 (_file "place_route/led_test_pnr.netlist"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:16")
+                    (_timespec "2023-12-13T10:56:02")
                 )
                 (_file "place_route/prr.db"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:16")
+                    (_timespec "2023-12-13T10:56:02")
                 )
             )
         )
@@ -190,22 +190,22 @@
             (_attribute _click_to_run (_switch ON))
         )
         (_command cmd_report_post_pnr_timing
-            (_gci_state (_integer 3))
+            (_gci_state (_integer 2))
             (_attribute _auto_exe_lock (_switch OFF))
             (_db_output
                 (_file "report_timing/led_test_rtp.adf"
                     (_format adif)
-                    (_timespec "2023-12-12T18:39:19")
+                    (_timespec "2023-12-13T10:56:05")
                 )
             )
             (_output
                 (_file "report_timing/led_test.rtr"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:19")
+                    (_timespec "2023-12-13T10:56:05")
                 )
                 (_file "report_timing/rtr.db"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:19")
+                    (_timespec "2023-12-13T10:56:05")
                 )
             )
         )
@@ -225,23 +225,23 @@
     )
     (_task tsk_gen_bitstream
         (_command cmd_gen_bitstream
-            (_gci_state (_integer 3))
+            (_gci_state (_integer 2))
             (_output
                 (_file "generate_bitstream/led_test.sbit"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:23")
+                    (_timespec "2023-12-13T10:56:09")
                 )
                 (_file "generate_bitstream/led_test.smsk"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:23")
+                    (_timespec "2023-12-13T10:56:09")
                 )
                 (_file "generate_bitstream/led_test.bgr"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:23")
+                    (_timespec "2023-12-13T10:56:09")
                 )
                 (_file "generate_bitstream/bgr.db"
                     (_format text)
-                    (_timespec "2023-12-12T18:39:23")
+                    (_timespec "2023-12-13T10:56:09")
                 )
             )
         )
diff --git a/source/source/async.v b/source/source/async.v
deleted file mode 100644
index baba942..0000000
--- a/source/source/async.v
+++ /dev/null
@@ -1,202 +0,0 @@
-////////////////////////////////////////////////////////
-// RS-232 RX and TX module
-// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
-
-// The RS-232 settings are fixed
-// TX: 8-bit data, 2 stop, no-parity
-// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
-
-//`define SIMULATION   // in this mode, TX outputs one bit per clock cycle
-                       // and RX receives one bit per clock cycle (for fast simulations)
-
-////////////////////////////////////////////////////////
-module async_transmitter(
-	input clk,
-	input TxD_start,
-	input [7:0] TxD_data,
-	output TxD,
-	output TxD_busy
-);
-
-// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
-// TxD_data is latched so that it doesn't have to stay valid while it is being sent
-
-parameter ClkFrequency = 50000000;	// 50MHz
-parameter Baud = 115200;
-
-generate
-	if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
-endgenerate
-
-////////////////////////////////
-`ifdef SIMULATION
-wire BitTick = 1'b1;  // output one bit per clock cycle
-`else
-wire BitTick;
-BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
-`endif
-
-reg [3:0] TxD_state = 0;
-wire TxD_ready = (TxD_state==0);
-assign TxD_busy = ~TxD_ready;
-
-reg [7:0] TxD_shift = 0;
-always @(posedge clk)
-begin
-	if(TxD_ready & TxD_start)
-		TxD_shift <= TxD_data;
-	else
-	if(TxD_state[3] & BitTick)
-		TxD_shift <= (TxD_shift >> 1);
-
-	case(TxD_state)
-		4'b0000: if(TxD_start) TxD_state <= 4'b0100;
-		4'b0100: if(BitTick) TxD_state <= 4'b1000;  // start bit
-		4'b1000: if(BitTick) TxD_state <= 4'b1001;  // bit 0
-		4'b1001: if(BitTick) TxD_state <= 4'b1010;  // bit 1
-		4'b1010: if(BitTick) TxD_state <= 4'b1011;  // bit 2
-		4'b1011: if(BitTick) TxD_state <= 4'b1100;  // bit 3
-		4'b1100: if(BitTick) TxD_state <= 4'b1101;  // bit 4
-		4'b1101: if(BitTick) TxD_state <= 4'b1110;  // bit 5
-		4'b1110: if(BitTick) TxD_state <= 4'b1111;  // bit 6
-		4'b1111: if(BitTick) TxD_state <= 4'b0010;  // bit 7
-		4'b0010: if(BitTick) TxD_state <= 4'b0011;  // stop1
-		4'b0011: if(BitTick) TxD_state <= 4'b0000;  // stop2
-		default: if(BitTick) TxD_state <= 4'b0000;
-	endcase
-end
-
-assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);  // put together the start, data and stop bits
-endmodule
-
-
-////////////////////////////////////////////////////////
-module async_receiver(
-	input clk,
-	input RxD,
-	output reg RxD_data_ready = 0,
-	output reg [7:0] RxD_data = 0,  // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
-
-	// We also detect if a gap occurs in the received stream of characters
-	// That can be useful if multiple characters are sent in burst
-	//  so that multiple characters can be treated as a "packet"
-	output RxD_idle,  // asserted when no data has been received for a while
-	output reg RxD_endofpacket = 0  // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
-);
-
-parameter ClkFrequency = 25000000; // 25MHz
-parameter Baud = 115200;
-
-parameter Oversampling = 8;  // needs to be a power of 2
-// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
-// 8 times oversampling by default, use 16 for higher quality reception
-
-generate
-	if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
-	if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
-endgenerate
-
-////////////////////////////////
-reg [3:0] RxD_state = 0;
-
-`ifdef SIMULATION
-wire RxD_bit = RxD;
-wire sampleNow = 1'b1;  // receive one bit per clock cycle
-
-`else
-wire OversamplingTick;
-BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
-
-// synchronize RxD to our clk domain
-reg [1:0] RxD_sync = 2'b11;
-always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
-
-// and filter it
-reg [1:0] Filter_cnt = 2'b11;
-reg RxD_bit = 1'b1;
-
-always @(posedge clk)
-if(OversamplingTick)
-begin
-	if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
-	else 
-	if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
-
-	if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
-	else
-	if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
-end
-
-// and decide when is the good time to sample the RxD line
-function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
-localparam l2o = log2(Oversampling);
-reg [l2o-2:0] OversamplingCnt = 0;
-always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
-wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
-`endif
-
-// now we can accumulate the RxD bits in a shift-register
-always @(posedge clk)
-case(RxD_state)
-	4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif;  // start bit found?
-	4'b0001: if(sampleNow) RxD_state <= 4'b1000;  // sync start bit to sampleNow
-	4'b1000: if(sampleNow) RxD_state <= 4'b1001;  // bit 0
-	4'b1001: if(sampleNow) RxD_state <= 4'b1010;  // bit 1
-	4'b1010: if(sampleNow) RxD_state <= 4'b1011;  // bit 2
-	4'b1011: if(sampleNow) RxD_state <= 4'b1100;  // bit 3
-	4'b1100: if(sampleNow) RxD_state <= 4'b1101;  // bit 4
-	4'b1101: if(sampleNow) RxD_state <= 4'b1110;  // bit 5
-	4'b1110: if(sampleNow) RxD_state <= 4'b1111;  // bit 6
-	4'b1111: if(sampleNow) RxD_state <= 4'b0010;  // bit 7
-	4'b0010: if(sampleNow) RxD_state <= 4'b0000;  // stop bit
-	default: RxD_state <= 4'b0000;
-endcase
-
-always @(posedge clk)
-if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
-
-//reg RxD_data_error = 0;
-always @(posedge clk)
-begin
-	RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit);  // make sure a stop bit is received
-	//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit);  // error if a stop bit is not received
-end
-
-`ifdef SIMULATION
-assign RxD_idle = 0;
-`else
-reg [l2o+1:0] GapCnt = 0;
-always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
-assign RxD_idle = GapCnt[l2o+1];
-always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
-`endif
-
-endmodule
-
-
-////////////////////////////////////////////////////////
-// dummy module used to be able to raise an assertion in Verilog
-module ASSERTION_ERROR();
-endmodule
-
-
-////////////////////////////////////////////////////////
-module BaudTickGen(
-	input clk, enable,
-	output tick  // generate a tick at the specified baud rate * oversampling
-);
-parameter ClkFrequency = 25000000;
-parameter Baud = 115200;
-parameter Oversampling = 1;
-
-function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
-localparam AccWidth = log2(ClkFrequency/Baud)+8;  // +/- 2% max timing error over a byte
-reg [AccWidth:0] Acc = 0;
-localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth));  // this makes sure Inc calculation doesn't overflow
-localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
-always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
-assign tick = Acc[AccWidth];
-endmodule
-
-
-////////////////////////////////////////////////////////