diff --git a/ipcore/ttl_pll/ttl_pll.idf b/ipcore/ttl_pll/ttl_pll.idf
new file mode 100644
index 0000000..56f37eb
--- /dev/null
+++ b/ipcore/ttl_pll/ttl_pll.idf
@@ -0,0 +1,641 @@
+
+
+
+ Pango
+ 021001
+ PLL
+ Logos PLL
+ 1.5
+ ttl_pll
+ Logos
+ PGL22G
+ MBG324
+ -6
+ IP Compiler
+
+
+
+ STATIC_DUTY2_basicPage
+ 16
+
+
+ CLKOUT2_EN_advancedPage
+ false
+
+
+ FEEDBACK_DELAY_VALUE_basicPage
+ 0.000
+ 3
+
+
+ DEVICE_PGL35
+ false
+
+
+ CLKOUT0_GATE_EN_advancedPage
+ false
+
+
+ CLK_CAS1_EN_advancedPage
+ false
+
+
+ STATIC_RATIO4_basicPage
+ 16
+
+
+ CLKOUT0_EN_basicPage
+ true
+
+
+ STATIC_DUTYF_basicPage
+ 24
+
+
+ CLKIN_BYPASS_EN_basicPage
+ false
+
+
+ CLK_CAS4_EN_basicPage
+ false
+
+
+ CLK_CAS4_EN_advancedPage
+ false
+
+
+ CLKOUT1_REQ_FREQ_basicPage
+ 50.0000
+ 4
+
+
+ FBMODE_advancedPage
+ false
+
+
+ CLKOUT2_REQ_DUTY_basicPage
+ 50.0000
+ 4
+
+
+ STATIC_DUTY3_advancedPage
+ 16
+
+
+ CLKOUT1_REQ_PHASE_basicPage
+ 0.0000
+ 4
+
+
+ CLKOUT0_EXT_GATE_EN_basicPage
+ false
+
+
+ STATIC_DUTY1_basicPage
+ 16
+
+
+ FBMODE_basicPage
+ false
+
+
+ CLKOUT1_EN_basicPage
+ false
+
+
+ CLKOUT0_REQ_PHASE_basicPage
+ 0.0000
+ 4
+
+
+ CLK_CAS2_EN_advancedPage
+ false
+
+
+ DYNAMIC_LOOP_EN_advancedPage
+ false
+
+
+ STATIC_DUTY2_advancedPage
+ 16
+
+
+ CLKOUT0_EXT_GATE_EN_advancedPage
+ false
+
+
+ FBDIV_SEL_advancedPage
+ 0
+
+
+ CLKOUT1_GATE_EN_basicPage
+ false
+
+
+ DYNAMIC_RATIOI_EN_advancedPage
+ false
+
+
+ DYNAMIC_RATIOM_EN_advancedPage
+ false
+
+
+ MODE
+ false
+
+
+ CLKOUT4_GATE_EN_advancedPage
+ false
+
+
+ STATIC_PHASE0_advancedPage
+ 16
+
+
+ DYNAMIC_PHASE3_EN_advancedPage
+ false
+
+
+ LOOP_MAPPING_EN_advancedPage
+ false
+
+
+ CLKIN_SEL_ENABLE_advancedPage
+ false
+
+
+ DYNAMIC_DUTY1_EN_advancedPage
+ false
+
+
+ STATIC_PHASE1_advancedPage
+ 16
+
+
+ DYNAMIC_PHASE4_EN_advancedPage
+ false
+
+
+ PFDEN_EN_advancedPage
+ false
+
+
+ DEVICE_PGL22
+ true
+
+
+ STATIC_RATIOM_basicPage
+ 1
+
+
+ FB_MODE_advancedPage
+ 0
+
+
+ STATIC_RATIO2_basicPage
+ 16
+
+
+ CLKIN_SEL_ENABLE_basicPage
+ false
+
+
+ CLKOUT5_SEL_advancedPage
+ 0
+
+
+ CLKSWITCH_FLAG_ENABLE_advancedPage
+ false
+
+
+ DEVICE_PGL12
+ false
+
+
+ STATIC_PHASE4_basicPage
+ 16
+
+
+ SHOW_SETTING_EN_basicPage
+ false
+
+
+ STATIC_PHASE3_basicPage
+ 16
+
+
+ FBDIV_SEL_basicPage
+ 0
+
+
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+ STATIC_RATIOM_advancedPage
+ 1
+
+
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+ 16
+
+
+ CLKOUT4_EN_basicPage
+ false
+
+
+ CLKOUT0_REQ_FREQ_basicPage
+ 50.0000
+ 4
+
+
+ CLK_CAS3_EN_advancedPage
+ false
+
+
+ STATIC_RATIOF_basicPage
+ 24
+
+
+ FEEDBACK_DELAY_ENABLE_advancedPage
+ false
+
+
+ DYNAMIC_RATIO3_EN_advancedPage
+ false
+
+
+ FEEDBACK_DELAY_ENABLE_basicPage
+ false
+
+
+ STATIC_DUTY0_advancedPage
+ 16
+
+
+ STATIC_DUTY1_advancedPage
+ 16
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+
+ CLKOUT0_GATE_EN_basicPage
+ false
+
+
+ RST_ENABLE_basicPage
+ false
+
+
+ DYNAMIC_RATIO1_EN_advancedPage
+ false
+
+
+ CLKOUT5_GATE_EN_advancedPage
+ false
+
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+ CLKOUT3_REQ_DUTY_basicPage
+ 50.0000
+ 4
+
+
+ STATIC_PHASE2_basicPage
+ 16
+
+
+ CLKOUT2_GATE_EN_advancedPage
+ false
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+ CLKOUT1_GATE_EN_advancedPage
+ false
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+
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+ false
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+ VCODIV2_ENABLE_advancedPage
+ false
+
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+ DYNAMIC_CLKIN_EN_advancedPage
+ false
+
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+ 16
+
+
+ RST_ENABLE_advancedPage
+ false
+
+
+ CLKIN_FREQ_advancedPage
+ 50.0000
+ 4
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+
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+ 16
+
+
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+ 12
+
+
+ STATIC_PHASE2_advancedPage
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+
+
+ PLL_PWD_ENABLE_basicPage
+ false
+
+
+ STATIC_PHASE1_basicPage
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+
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+ false
+
+
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+ false
+
+
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+ false
+
+
+ CLKOUT4_GATE_EN_basicPage
+ false
+
+
+ CLKOUT4_REQ_PHASE_basicPage
+ 0.0000
+ 4
+
+
+ CLKOUT3_EN_advancedPage
+ false
+
+
+ STATIC_DUTY0_basicPage
+ 12
+
+
+ DYNAMIC_DUTY4_EN_advancedPage
+ false
+
+
+ PLL_PWD_ENABLE_advancedPage
+ false
+
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+ CLKOUT3_REQ_FREQ_basicPage
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+ 4
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+ 0
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+ false
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+ false
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+ false
+
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+ false
+
+
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+ 2
+
+
+ CLKOUT2_EN_basicPage
+ false
+
+
+ BANDWIDTH_advancedPage
+ OPTIMIZED
+
+
+ CLKOUT4_REQ_DUTY_basicPage
+ 50.0000
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+
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+ false
+
+
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+ 0.0000
+ 4
+
+
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+ 16
+
+
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+ 16
+
+
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+ 16
+
+
+ CLK_CAS3_EN_basicPage
+ false
+
+
+ STATIC_PHASE3_advancedPage
+ 16
+
+
+ CLKOUT0_EXT_EN_basicPage
+ false
+
+
+ CLKOUT0_EN_advancedPage
+ true
+
+
+ STATIC_PHASE0_basicPage
+ 16
+
+
+ STATIC_RATIOI_basicPage
+ 2
+
+
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+ false
+
+
+ CLKOUT1_EN_advancedPage
+ false
+
+
+ STATIC_RATIO3_advancedPage
+ 16
+
+
+ CLKOUT3_REQ_PHASE_basicPage
+ 0.0000
+ 4
+
+
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+ false
+
+
+ CLKOUT2_REQ_FREQ_basicPage
+ 50.0000
+ 4
+
+
+ CLKOUT0_REQ_DUTY_basicPage
+ 50.0000
+ 4
+
+
+ CLKOUT0_EXT_EN_advancedPage
+ false
+
+
+ CLKIN_SEL_EN_ENABLE_basicPage
+ false
+
+
+ CLKIN_SEL_EN_ENABLE_advancedPage
+ false
+
+
+ DYNAMIC_PHASE_EN_advancedPage
+ false
+
+
+ CLK_CAS2_EN_basicPage
+ false
+
+
+ CLKOUT3_GATE_EN_advancedPage
+ false
+
+
+ FEEDBACK_DELAY_VALUE_advancedPage
+ 0.000
+ 3
+
+
+ CLKSWITCH_FLAG_ENABLE_basicPage
+ false
+
+
+ CLKOUT1_REQ_DUTY_basicPage
+ 50.0000
+ 4
+
+
+ BANDWIDTH_basicPage
+ OPTIMIZED
+
+
+ CLK_CAS1_EN_basicPage
+ false
+
+
+ DYNAMIC_PHASE2_EN_advancedPage
+ false
+
+
+ STATIC_RATIO1_basicPage
+ 16
+
+
+ STATIC_RATIO4_advancedPage
+ 16
+
+
+ CLKOUT4_REQ_FREQ_basicPage
+ 50.0000
+ 4
+
+
+ CLKIN_FREQ_basicPage
+ 50.0000
+ 4
+
+
+ CLKOUT2_GATE_EN_basicPage
+ false
+
+
+ DYNAMIC_RATIO2_EN_advancedPage
+ false
+
+
+ DYNAMIC_DUTY0_EN_advancedPage
+ false
+
+
+ DYNAMIC_CLKIN_EN_basicPage
+ false
+
+
+ MODE_CFG
+ 0
+
+
+ DYNAMIC_RATIO4_EN_advancedPage
+ false
+
+
+
+
+ clkin1
+ clkin1
+ input
+ left
+
+
+ pll_lock
+ pll_lock
+ output
+ right
+
+
+ clkout0
+ clkout0
+ output
+ right
+
+
+
+
+
+
+
diff --git a/led_test.pds b/led_test.pds
index ced14ee..7929108 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
- (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri Dec 15 22:18:27 2023")
+ (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Dec 30 17:32:33 2023")
(_version "1.0.5")
(_status "initial")
(_project
@@ -25,9 +25,9 @@
(_format verilog)
(_timespec "2023-12-13T15:21:23")
)
- (_file "source/src/top.v" + "Top"
+ (_file "source/src/top.v" + "Top:"
(_format verilog)
- (_timespec "2023-12-15T20:12:24")
+ (_timespec "2023-12-30T12:39:05")
)
(_file "source/src/uart_tx.v"
(_format verilog)
@@ -49,6 +49,18 @@
(_format verilog)
(_timespec "2023-12-15T22:06:08")
)
+ (_file "source/src/src_ttl_parser.v"
+ (_format verilog)
+ (_timespec "2023-12-30T15:38:08")
+ )
+ (_file "source/src/src_timecode.v"
+ (_format verilog)
+ (_timespec "2023-12-30T16:15:29")
+ )
+ (_file "source/src/des_ttl_generator.v"
+ (_format verilog)
+ (_timespec "2023-12-30T17:32:32")
+ )
)
)
(_widget wgt_my_ips_src
@@ -59,6 +71,9 @@
(_timespec "2023-12-14T21:34:50")
)
)
+ (_ip "ipcore/ttl_pll/ttl_pll.idf"
+ (_timespec "2023-12-30T15:00:33")
+ )
)
)
(_widget wgt_import_logic_con_file
@@ -104,21 +119,21 @@
)
(_task tsk_compile
(_command cmd_compile
- (_gci_state (_integer 2))
+ (_gci_state (_integer 3))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
- (_timespec "2023-12-15T22:11:12")
+ (_timespec "2023-12-30T14:43:56")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
- (_timespec "2023-12-15T22:11:12")
+ (_timespec "2023-12-30T14:43:56")
)
(_file "compile/cmr.db"
(_format text)
- (_timespec "2023-12-15T22:11:12")
+ (_timespec "2023-12-30T14:43:56")
)
)
)
@@ -128,27 +143,27 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
- (_gci_state (_integer 2))
+ (_gci_state (_integer 3))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
- (_timespec "2023-12-15T22:11:14")
+ (_timespec "2023-12-30T14:53:59")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
- (_timespec "2023-12-15T22:11:14")
+ (_timespec "2023-12-30T14:53:59")
)
(_file "synthesize/Top.snr"
(_format text)
- (_timespec "2023-12-15T22:11:14")
+ (_timespec "2023-12-30T14:53:59")
)
(_file "synthesize/snr.db"
(_format text)
- (_timespec "2023-12-15T22:11:14")
+ (_timespec "2023-12-30T14:53:59")
)
)
)
@@ -165,7 +180,7 @@
)
(_task tsk_devmap
(_command cmd_devmap
- (_gci_state (_integer 5))
+ (_gci_state (_integer 0))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
diff --git a/source/src/des_ttl_generator.v b/source/src/des_ttl_generator.v
new file mode 100644
index 0000000..b3f5012
--- /dev/null
+++ b/source/src/des_ttl_generator.v
@@ -0,0 +1,122 @@
+module des_ttl_generator #(
+ parameter REG_START_ADD = 0
+) (
+ input clk, //clock input
+ input rst_n, //asynchronous reset input, low active
+
+ //regbus interface
+ output reg [31:0] addr,
+ input [31:0] wr_data,
+ input wr_en,
+
+ inout wire [31:0] rd_data, //received serial data
+ // 输入
+ input signal_in,
+ //输出
+ output reg ttloutput //ttl原始数据
+);
+ //
+ // @功能:
+ // 1. 功能:同步输出,脉冲输出
+ // 2. 输出脉冲
+ // 3. 输出脉冲时长可调
+ // 4. 输出极性可调
+ //
+ //
+ // @寄存器列表:
+ // 地址 读写 默认 描述
+ // 0x00 wr 0x0 模式 0:同步输出 1:脉冲输出
+ // 0x01 wr 0x0 脉冲模式-脉冲触发方式 0:上升沿 1:下降沿触发
+ // 0x02 wr 0x0 脉冲模式-有效电平长度: 0~0xffffffff
+ // 0x03 wr 0x0 输出极性 0:正极性 1:极性翻转
+ //
+
+ parameter ADD_NUM = 5; //寄存器数量
+
+ parameter REG_FUNC_ADD = REG_START_ADD + 0; //功能寄存器地址
+ parameter REG_PULSE_MODE_ADD = REG_START_ADD + 1; //脉冲模式寄存器地址
+ parameter REG_PULSE_MODE_RISE_FALL_ADD = REG_START_ADD + 2; //脉冲模式-脉冲触发方式寄存器地址
+ parameter REG_PULSE_MODE_VALID_LEN_ADD = REG_START_ADD + 3; //脉冲模式-有效电平长度寄存器地址
+ parameter REG_OUTPUT_POLARITY_ADD = REG_START_ADD + 4; //输出极性寄存器地址
+
+ reg ttl_origin_output; //ttl原始信号输出
+ wire ttl_after_process_output; //ttl处理后信号输出
+
+ assign signal_in_a = signal_in; //信号输入
+ reg signal_in_b = 0; //信号输入延迟一周期
+
+
+
+ /*******************************************************************************
+ * 寄存器读写 *
+ *******************************************************************************/
+ parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址
+ reg [31:0] register[REG_START_ADD:REG_END_ADD];
+ integer i;
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ for (i = 0; i < ADD_NUM; i = i + 1) begin
+ register[i] <= 0;
+ end
+ end else begin
+ if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data;
+ end
+ end
+ assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz;
+
+
+
+ /*******************************************************************************
+ * signal_a and signal_b *
+ *******************************************************************************/
+ // signal_in 脉冲信号捕获
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ signal_in_b <= 0;
+ end else begin
+ signal_in_b <= signal_in_a;
+ end
+ end
+ /*******************************************************************************
+ * 脉冲模式输出 *
+ *******************************************************************************/
+ // 电平计数
+ reg [31:0] signal_output_duration_cnt;
+ assign signal_src_trigger = (register[REG_PULSE_MODE_RISE_FALL_ADD] == 0) ? (signal_in_a & ~signal_in_b) : (~signal_in_a & signal_in_b);
+ // 通过计数输出波形
+ assign ttl_after_process_output = (signal_output_duration_cnt < register[REG_PULSE_MODE_VALID_LEN_ADD]) ? 1 : 0;
+ // 脉冲计数
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ signal_output_duration_cnt <= 0;
+ end else begin
+ // 脉冲模式
+ if (register[REG_FUNC_ADD] == 1) begin
+ if (signal_src_trigger == 1) begin
+ signal_output_duration_cnt <= 0;
+ end else begin
+ signal_output_duration_cnt <= signal_output_duration_cnt + 1;
+ end
+ end // 非脉冲模式
+ else begin
+ signal_output_duration_cnt <= 0;
+ end
+ end
+ end
+ /*******************************************************************************
+ * 信号输出控制 *
+ *******************************************************************************/
+ reg ttloutput;
+ always @(*) begin
+ case (register[REG_FUNC_ADD])
+ 0: begin
+ ttloutput = (register[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_origin_output : !ttl_origin_output;
+ end
+ 1: begin
+ ttloutput = (register[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_after_process_output : !ttl_after_process_output;
+ end
+ default: ttloutput = 0;
+ endcase
+ end
+
+endmodule
diff --git a/source/src/src_genlock.v b/source/src/src_genlock.v
new file mode 100644
index 0000000..e69de29
diff --git a/source/src/src_timecode.v b/source/src/src_timecode.v
new file mode 100644
index 0000000..e69de29
diff --git a/source/src/src_ttl_parser.v b/source/src/src_ttl_parser.v
new file mode 100644
index 0000000..cd767fc
--- /dev/null
+++ b/source/src/src_ttl_parser.v
@@ -0,0 +1,131 @@
+module src_ttl_parser #(
+ parameter REG_START_ADD = 0
+) (
+ input clk, //clock input
+ input rst_n, //asynchronous reset input, low active
+
+ //regbus interface
+ output reg [31:0] addr,
+ input [31:0] wr_data,
+ input wr_en,
+
+ inout wire [31:0] rd_data, //received serial data
+ // 输入
+ input ttlin,
+ //输出
+ output wire ttl_output //ttl原始数据
+);
+ //
+ // @功能:
+ // 1. 计算ttl频率
+ // 2. 转发ttl信号
+ // 3. 分频倍频
+ //
+ // @寄存器列表:
+ // 地址 读写 默认 描述
+ // 0x00 r 0x0 function 0:原始信号输出 1:频率信号源
+ // 0x01 r 0x0 freq //一个周期的计数，单位为 1/50M s
+ // 0x02 wr 0x0 pll_mul //暂不支持
+ // 0x03 wr 0x0 pll_div
+ // 0x04 wr 0x0 [0]:信号源是上升沿触发，还是下降沿触发
+ //
+
+
+ reg ttl_origin_output; //ttl原始信号输出
+ reg ttl_after_process_output; //ttl处理后信号输出
+
+
+ /*******************************************************************************
+ * 寄存器读写 *
+ *******************************************************************************/
+
+ parameter ADD_NUM = 5; //寄存器数量
+ parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址
+ reg [31:0] register[REG_START_ADD:REG_END_ADD];
+ integer i;
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ for (i = 0; i < ADD_NUM; i = i + 1) begin
+ register[i] <= 0;
+ end
+ end else begin
+ if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data;
+ end
+ end
+ assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz;
+
+ parameter REG_FUNC_ADD = REG_START_ADD + 0;
+ parameter REG_FREQ_ADD = REG_START_ADD + 1;
+ parameter REG_PLL_MUL_ADD = REG_START_ADD + 2;
+ parameter REG_PLL_DIV_ADD = REG_START_ADD + 3;
+ parameter REG_TTL_EDGE_ADD = REG_START_ADD + 4;
+
+ /*******************************************************************************
+ * ttl输出路径选择 *
+ *******************************************************************************/
+
+ assign ttl_output = (register[REG_FUNC_ADD] == 0) ? ttl_origin_output : ttl_after_process_output;
+
+ /*******************************************************************************
+ * 原始信号输出 *
+ *******************************************************************************/
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ ttl_origin_output <= 0;
+ end else begin
+ ttl_origin_output <= ttlin;
+ end
+ end
+
+ /*******************************************************************************
+ * ttl_in_last信号捕获 *
+ *******************************************************************************/
+ reg ttl_in_last;
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ ttl_in_last <= 0;
+ end else begin
+ ttl_in_last <= ttlin;
+ end
+ end
+
+
+ /*******************************************************************************
+ * 频率探测 *
+ *******************************************************************************/
+ reg [31:0] ttl_freq_cnt;
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ ttl_freq_cnt <= 0;
+ end else begin
+ if (ttlin && !ttl_in_last) begin
+ register[REG_FREQ_ADD] <= ttl_freq_cnt;
+ ttl_freq_cnt <= 0;
+ end
+ if (ttl_freq_cnt != 32'hffff_ffff_ffff_ffff) begin
+ ttl_freq_cnt <= ttl_freq_cnt + 1;
+ end
+ end
+ end
+
+ /*******************************************************************************
+ * 分频 *
+ *******************************************************************************/
+ reg [31:0] ttl_in_cnt;
+ always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ ttl_in_cnt <= 0;
+ end else begin
+ if (ttlin && !ttl_in_last) begin
+ if (ttl_in_cnt <= register[REG_PLL_MUL_ADD]) begin
+ ttl_in_cnt <= ttl_in_cnt + 1;
+ end else begin
+ ttl_in_cnt <= 0;
+ ttl_after_process_output <= 1;
+ end
+ end else begin
+ ttl_after_process_output <= 0;
+ end
+ end
+ end
+endmodule
diff --git a/source/src/top.v b/source/src/top.v
index 996324b..0ceaf20 100644
--- a/source/src/top.v
+++ b/source/src/top.v
@@ -16,9 +16,27 @@ module Top (
- monitor_line monitor_line_usb_serial_rx(sys_clk, rst_n, usb_serial_rx, test_io[4]);
+ monitor_line monitor_line_usb_serial_rx (
+ sys_clk,
+ rst_n,
+ usb_serial_rx,
+ test_io[4]
+ );
assign test_io[3] = usb_serial_tx;
-// assign test_io[3] = inclkpll_clk0out;
+ // assign test_io[3] = inclkpll_clk0out;
+
+ src_ttl_parser src_ttl_parser_inst (
+ .clk(),
+ .rst_n(),
+ //regbus interface
+ .addr(),
+ .wr_data(),
+ .wr_en(),
+ .rd_data(),
+ .ttlin(),
+ .ttl_origin_data(),
+ .ttl_after_process_data()
+ );
endmodule