diff --git a/led_test.pds b/led_test.pds index b53cb76..3bebe77 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Jan 7 20:01:57 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 14:58:21 2024") (_version "1.0.5") (_status "initial") (_project @@ -27,7 +27,7 @@ ) (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-07T14:49:59") + (_timespec "2024-01-08T14:52:29") ) (_file "source/src/uart_tx.v" (_format verilog) @@ -51,15 +51,11 @@ ) (_file "source/src/src_ttl_parser.v" (_format verilog) - (_timespec "2023-12-30T15:38:08") + (_timespec "2024-01-08T14:55:25") ) (_file "source/src/src_timecode.v" (_format verilog) - (_timespec "2023-12-30T20:50:11") - ) - (_file "source/src/des_ttl_generator.v" - (_format verilog) - (_timespec "2023-12-31T17:25:29") + (_timespec "2024-01-08T14:55:20") ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) @@ -71,11 +67,11 @@ ) (_file "source/src/zutils/zutils_register.v" (_format verilog) - (_timespec "2024-01-07T15:54:33") + (_timespec "2024-01-08T14:54:46") ) (_file "source/src/zutils/zutils_multiplexer_4t1.v" (_format verilog) - (_timespec "2023-12-31T17:16:29") + (_timespec "2024-01-08T12:37:43") ) (_file "source/src/zutils/zutils_debug_led.v" (_format verilog) @@ -89,6 +85,22 @@ (_format verilog) (_timespec "2024-01-07T18:36:41") ) + (_file "source/src/zutils/zutils_multiplexer_16t1.v" + (_format verilog) + (_timespec "2024-01-08T12:43:05") + ) + (_file "source/src/output/ttl_output.v" + (_format verilog) + (_timespec "2024-01-08T14:55:31") + ) + (_file "source/src/zutils/zutils_pwm_generator.v" + (_format verilog) + (_timespec "2024-01-08T10:07:08") + ) + (_file "source/src/rd_data_router.v" + (_format verilog) + (_timespec "2024-01-08T14:58:15") + ) ) ) (_widget wgt_my_ips_src @@ -148,17 +160,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-07T20:01:29") + (_timespec "2024-01-08T14:58:18") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-07T20:01:29") + (_timespec "2024-01-08T14:58:18") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-07T20:01:29") + (_timespec "2024-01-08T14:58:19") ) ) ) @@ -168,27 +180,13 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 2)) + (_gci_state (_integer 1)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) - (_db_output - (_file "synthesize/Top_syn.adf" - (_format adif) - (_timespec "2024-01-07T20:01:33") - ) - ) (_output - (_file "synthesize/Top_syn.vm" - (_format structural_verilog) - (_timespec "2024-01-07T20:01:33") - ) - (_file "synthesize/Top.snr" - (_format text) - (_timespec "2024-01-07T20:01:33") - ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-07T20:01:33") + (_timespec "2024-01-08T14:58:21") ) ) ) @@ -205,27 +203,7 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 2)) - (_db_output - (_file "device_map/Top_map.adf" - (_format adif) - (_timespec "2024-01-07T20:01:36") - ) - ) - (_output - (_file "device_map/Top_dmr.prt" - (_format text) - (_timespec "2024-01-07T20:01:36") - ) - (_file "device_map/Top.dmr" - (_format text) - (_timespec "2024-01-07T20:01:36") - ) - (_file "device_map/dmr.db" - (_format text) - (_timespec "2024-01-07T20:01:36") - ) - ) + (_gci_state (_integer 0)) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) @@ -242,39 +220,7 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 2)) - (_db_output - (_file "place_route/Top_pnr.adf" - (_format adif) - (_timespec "2024-01-07T20:01:46") - ) - ) - (_output - (_file "place_route/Top.prr" - (_format text) - (_timespec "2024-01-07T20:01:46") - ) - (_file "place_route/Top_prr.prt" - (_format text) - (_timespec "2024-01-07T20:01:46") - ) - (_file "place_route/clock_utilization.txt" - (_format text) - (_timespec "2024-01-07T20:01:46") - ) - (_file "place_route/Top_plc.adf" - (_format adif) - (_timespec "2024-01-07T20:01:43") - ) - (_file "place_route/Top_pnr.netlist" - (_format text) - (_timespec "2024-01-07T20:01:46") - ) - (_file "place_route/prr.db" - (_format text) - (_timespec "2024-01-07T20:01:47") - ) - ) + (_gci_state (_integer 0)) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -283,24 +229,8 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 2)) + (_gci_state (_integer 0)) (_attribute _auto_exe_lock (_switch OFF)) - (_db_output - (_file "report_timing/Top_rtp.adf" - (_format adif) - (_timespec "2024-01-07T20:01:51") - ) - ) - (_output - (_file "report_timing/Top.rtr" - (_format text) - (_timespec "2024-01-07T20:01:51") - ) - (_file "report_timing/rtr.db" - (_format text) - (_timespec "2024-01-07T20:01:51") - ) - ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -318,25 +248,7 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 2)) - (_output - (_file "generate_bitstream/Top.sbit" - (_format text) - (_timespec "2024-01-07T20:01:57") - ) - (_file "generate_bitstream/Top.smsk" - (_format text) - (_timespec "2024-01-07T20:01:57") - ) - (_file "generate_bitstream/Top.bgr" - (_format text) - (_timespec "2024-01-07T20:01:57") - ) - (_file "generate_bitstream/bgr.db" - (_format text) - (_timespec "2024-01-07T20:01:57") - ) - ) + (_gci_state (_integer 0)) ) ) ) diff --git a/source/src/config.v b/source/src/config.v new file mode 100644 index 0000000..9966975 --- /dev/null +++ b/source/src/config.v @@ -0,0 +1,22 @@ +//STM32寄存器地址 +`define REG_ADD_OFF_STM32 16'h0000 +`define REG_ADD_OFF_FPGA_TEST 16'h00020 +//控制中心寄存器地址 +`define REG_ADD_OFF_CONTROL_SENSOR 16'h00030 +//输入组件 +`define REG_ADD_OFF_TTLIN1 16'h0100 +`define REG_ADD_OFF_TTLIN2 16'h0110 +`define REG_ADD_OFF_TTLIN3 16'h0120 +`define REG_ADD_OFF_TTLIN4 16'h0130 +`define REG_ADD_OFF_TIMECODE_IN 16'h0140 +`define REG_ADD_OFF_GENLOCK_IN 16'h0150 +//输出组件 +`define REG_ADD_OFF_TTLOUT1 16'h0200 +`define REG_ADD_OFF_TTLOUT2 16'h0210 +`define REG_ADD_OFF_TTLOUT3 16'h0220 +`define REG_ADD_OFF_TTLOUT4 16'h0230 +`define REG_ADD_OFF_TIMECODE_OUT 16'h0240 +`define REG_ADD_OFF_GENLOCK_OUT 16'h0250 +`define REG_ADD_OFF_STM32_IF 16'h0260 +//调试组件 +`define REG_ADD_OFF_DEBUGER 16'h0300 diff --git a/source/src/des_ttl_generator.v b/source/src/des_ttl_generator.v deleted file mode 100644 index 456fd22..0000000 --- a/source/src/des_ttl_generator.v +++ /dev/null @@ -1,105 +0,0 @@ -// -// @功能: -// 1. 功能:同步输出,脉冲输出 -// 2. 输出脉冲 -// 3. 输出脉冲时长可调 -// 4. 输出极性可调 -// -module des_ttl_generator #( - parameter REG_START_ADD = 0 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //寄存器读写接口 - output [31:0] addr, - input [31:0] wr_data, - input wr_en, - inout wire [31:0] rd_data, - - input signal_in, //输入信号 - output ttloutput //ttl输出信号 -); - - - /******************************************************************************* - * 寄存器列表 * - *******************************************************************************/ - // - // 模式寄存器 - // [0] 0:同步输出 1:脉冲输出 - wire [31:0] reg_function; - - // - // 配置寄存器 - // [0] 脉冲输入时候触发信号 0:上升沿 1:下降沿触发 - // [1] 输出极性控制位 0:输出高电平 1:输出低电平 - // - wire [31:0] reg_config; - assign pluse_input_trigger_signal = reg_config[0]; - assign output_polarity = !reg_config[1]; - - // - // 脉冲模式-有效电平长度: - // 0~0xffffffff - // - wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff - - //脉冲输出 - wire pluse_output; - // 输入信号上升沿事件 - wire in_signal_rising_edge; - // 输入信号下降沿事件 - wire in_signal_falling_edge; - // 输入信号上升沿或下降沿事件 - wire in_signal_edge; - // 输出的脉冲触发信号的触发信号 - wire signal_src_trigger; - - assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge); - - zutils_register16 #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk(clk), - .rst_n(rst_n), - .addr(addr), - .wr_data(wr_data), - .wr_en(wr_en), - .rd_data(rd_data), - .reg0(reg_function), - .reg1(reg_config), - .reg2(reg_pulse_mode_valid_len) - ); - - zutils_edge_detecter _signal_in ( - .clk(clk), - .rst_n(rst_n), - .in_signal(signal_in), - .in_signal_rising_edge(in_signal_rising_edge), - .in_signal_falling_edge(in_signal_falling_edge), - .in_signal_edge(in_signal_edge) - ); - - zutils_pluse_generator _pluse_generator ( - .clk(clk), - .rst_n(rst_n), - .pluse_width(reg_pulse_mode_valid_len), - .trigger(signal_src_trigger), - .output_signal(ttl_after_process_output) - ); - - - assign output_signal0 = (output_polarity == 1) ? signal_in : !signal_in; - assign output_signal1 = (output_polarity == 1) ? ttl_after_process_output : !ttl_after_process_output; - - zutils_multiplexer_4t1 multiplexer_4t1 ( - .chooseindex(reg_function), - .signal0(output_signal0), - .signal1(output_signal1), - .signal2(0), - .signal3(0), - .signalout(ttloutput) - ); - -endmodule diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v new file mode 100644 index 0000000..a953761 --- /dev/null +++ b/source/src/output/ttl_output.v @@ -0,0 +1,152 @@ +// +// @功能: +// 1. 功能:同步输出,脉冲输出 +// 2. 输出脉冲 +// 3. 输出脉冲时长可调 +// 4. 输出极性可调 +// +module ttl_output #( + parameter REG_START_ADD = 0, + parameter TEST = 0 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //寄存器读写接口 + output [31:0] addr, + input [31:0] wr_data, + input wr_en, + output wire [31:0] rd_data, + + input [7:0] signal_in, + + output ttloutput, //ttl输出信号 + output ttloutput_state_led //ttl输出状态信号 +); + + + /******************************************************************************* + * 寄存器列表 * + *******************************************************************************/ + // + // 输入信号选择器 + // 0: 信号0 + // 1: 信号1 + // ... + // x: 信号x + + wire [31:0] reg_input_signal_select; + // + // 输出信号选择器 + // [0] + // 0:输出0 + // 1:输出1 + // 2:测试信号输出 + // 3:原始信号 + // 4:原始信号翻转输出 + // 5:脉冲输出 + // 6:脉冲信号翻转输出 + localparam REG1_INIT = TEST ? 2 : 0; + wire [31:0] reg_output_signal_select; + + // + // 配置寄存器 + // [0] 脉冲输入时候触发信号 0:上升沿 1:下降沿触发 + // + wire [31:0] reg_config; + assign pluse_input_trigger_signal = reg_config[0]; + // + // 脉冲模式-有效电平长度: + // 0~0xffffffff + // + wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff + + + zutils_register16 #( + .REG_START_ADD(REG_START_ADD), + .REG1_INIT(REG1_INIT) + ) _register ( + .clk(clk), + .rst_n(rst_n), + .addr(addr), + .wr_data(wr_data), + .wr_en(wr_en), + .rd_data(rd_data), + .reg0(reg_input_signal_select), + .reg1(reg_output_signal_select), + .reg2(reg_config), + .reg3(reg_pulse_mode_valid_len) + ); + + /******************************************************************************* + * 内部信号 * + *******************************************************************************/ + + //脉冲输出 + wire pluse_output; + // 输入信号上升沿事件 + wire in_signal_rising_edge; + // 输入信号下降沿事件 + wire in_signal_falling_edge; + // 输入信号上升沿或下降沿事件 + wire in_signal_edge; + // 输出的脉冲触发信号的触发信号 + wire signal_src_trigger; + + assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge); + + wire signal_in_choose; + zutils_multiplexer_16t1 _signal_select ( + .chooseindex(reg_input_signal_select), + .signal({8'b0, signal_in}), + .signalout(signal_in_choose) + ); + + + // 边沿检测 + zutils_edge_detecter _signal_in ( + .clk(clk), + .rst_n(rst_n), + .in_signal(signal_in_choose), + .in_signal_rising_edge(in_signal_rising_edge), + .in_signal_falling_edge(in_signal_falling_edge), + .in_signal_edge(in_signal_edge) + ); + + // 短脉冲，触发生成，长脉冲 + zutils_pluse_generator _pluse_generator ( + .clk(clk), + .rst_n(rst_n), + .pluse_width(reg_pulse_mode_valid_len), + .trigger(signal_src_trigger), + .output_signal(ttl_after_process_output) + ); + + zutils_pwm_generator #( + .SYS_CLOCK_FREQ(50000000), + .OUTPUT_FREQ(1000) + ) _test_signal_generator ( + .clk(clk), + .rst_n(rst_n), + .output_signal(test_signal_output) + ); + + + zutils_multiplexer_16t1 _signal_output_select ( + .chooseindex(reg_output_signal_select), + .signal({ + 8'b0, + /*7*/ 0, + /*6*/ 0, + /*5*/ ttl_after_process_output, + /*4*/ !ttl_after_process_output, + /*3*/ signal_in_choose, + /*2*/ test_signal_output, + /*1*/ 1, + /*0*/ 0 + }), + .signalout(ttloutput) + ); + assign ttloutput_state_led = ttloutput; + +endmodule diff --git a/source/src/rd_data_router.v b/source/src/rd_data_router.v new file mode 100644 index 0000000..6711ee1 --- /dev/null +++ b/source/src/rd_data_router.v @@ -0,0 +1,77 @@ +`include "config.v" +/* + * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud + * rx/tx pair where the rx clcken oversamples by 16x. + */ +module rd_data_router ( + input [31:0] addr, + + input [31:0] stm32_rd_data, + input [31:0] fpga_test_rd_data, + input [31:0] control_sensor_rd_data, + input [31:0] ttlin1_rd_data, + input [31:0] ttlin2_rd_data, + input [31:0] ttlin3_rd_data, + input [31:0] ttlin4_rd_data, + input [31:0] timecode_in_rd_data, + input [31:0] genlock_in_rd_data, + input [31:0] ttlout1_rd_data, + input [31:0] ttlout2_rd_data, + input [31:0] ttlout3_rd_data, + input [31:0] ttlout4_rd_data, + input [31:0] timecode_out_rd_data, + input [31:0] genlock_out_rd_data, + input [31:0] stm32_if_rd_data, + input [31:0] debuger_rd_data, + + output reg [31:0] rd_data_out +); + + // //STM32寄存器地址 + // localparam REG_ADD_OFF_STM32 = 16'h0000; + // localparam REG_ADD_OFF_FPGA_TEST = 16'h00020; + // //控制中心寄存器地址 + // localparam REG_ADD_OFF_CONTROL_SENSOR = 16'h00030; + // //输入组件 + // localparam REG_ADD_OFF_TTLIN1 = 16'h0100; + // localparam REG_ADD_OFF_TTLIN2 = 16'h0110; + // localparam REG_ADD_OFF_TTLIN3 = 16'h0120; + // localparam REG_ADD_OFF_TTLIN4 = 16'h0130; + // localparam REG_ADD_OFF_TIMECODE_IN = 16'h0140; + // localparam REG_ADD_OFF_GENLOCK_IN = 16'h0150; + // //输出组件 + // localparam REG_ADD_OFF_TTLOUT1 = 16'h0200; + // localparam REG_ADD_OFF_TTLOUT2 = 16'h0210; + // localparam REG_ADD_OFF_TTLOUT3 = 16'h0220; + // localparam REG_ADD_OFF_TTLOUT4 = 16'h0230; + // localparam REG_ADD_OFF_TIMECODE_OUT = 16'h0240; + // localparam REG_ADD_OFF_GENLOCK_OUT = 16'h0250; + // localparam REG_ADD_OFF_STM32_IF = 16'h0260; + // //调试组件 + // localparam REG_ADD_OFF_DEBUGER = 16'h0300; + + + always @(*) begin + case (addr >> 8) + // `REG_ADD_OFF_STM32 >> 8: rd_data_out = stm32_rd_data; + // `REG_ADD_OFF_FPGA_TEST >> 8: rd_data_out = fpga_test_rd_data; + // `REG_ADD_OFF_CONTROL_SENSOR >> 8: rd_data_out = control_sensor_rd_data; + // `REG_ADD_OFF_TTLIN1 >> 8: rd_data_out = ttlin1_rd_data; + // `REG_ADD_OFF_TTLIN2 >> 8: rd_data_out = ttlin2_rd_data; + // `REG_ADD_OFF_TTLIN3 >> 8: rd_data_out = ttlin3_rd_data; + // `REG_ADD_OFF_TTLIN4 >> 8: rd_data_out = ttlin4_rd_data; + // `REG_ADD_OFF_TIMECODE_IN >> 8: rd_data_out = timecode_in_rd_data; + // `REG_ADD_OFF_GENLOCK_IN >> 8: rd_data_out = genlock_in_rd_data; + // `REG_ADD_OFF_TTLOUT1 >> 8: rd_data_out = ttlout1_rd_data; + // `REG_ADD_OFF_TTLOUT2 >> 8: rd_data_out = ttlout2_rd_data; + // `REG_ADD_OFF_TTLOUT3 >> 8: rd_data_out = ttlout3_rd_data; + // `REG_ADD_OFF_TTLOUT4 >> 8: rd_data_out = ttlout4_rd_data; + // `REG_ADD_OFF_TIMECODE_OUT >> 8: rd_data_out = timecode_out_rd_data; + // `REG_ADD_OFF_GENLOCK_OUT >> 8: rd_data_out = genlock_out_rd_data; + // `REG_ADD_OFF_STM32_IF >> 8: rd_data_out = stm32_if_rd_data; + // `REG_ADD_OFF_DEBUGER >> 8: rd_data_out = debuger_rd_data; + default: rd_data_out = 0; + endcase + end + +endmodule diff --git a/source/src/src_timecode.v b/source/src/src_timecode.v index 7d08d49..8ef0be2 100644 --- a/source/src/src_timecode.v +++ b/source/src/src_timecode.v @@ -1,208 +1,208 @@ -module src_timecode_parser #( - parameter REG_START_ADD = 0 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //regbus interface - output reg [31:0] addr, - input [31:0] wr_data, - input wr_en, - - inout wire [31:0] rd_data, //received serial data - // 输入 - input timecode_signal_in, - //输出 - output wire timecode_signal_orgin_output, //ttl原始数据 - output wire timecode_freq_trigger_signal -); - - /******************************************************************************* - * 寄存器读写 * - *******************************************************************************/ - - // - // @功能: - // 1. 采样TIMECODE信号 - // 2. 转发TIMECODE信号 - // 3. TIMECODE信号成功解析 - // 4. TIMECODE采样计数 - // - // @寄存器列表: - // 地址 读写 默认 描述 - // 0x00 wr 0x0 timecode bit周期 - // 0x01 r 0x0 flag bit[0]:timecode_ready_flag - // 0x02 r 0x0 timecode [31:0] - // 0x03 r 0x0 timecode [63:32] - // 0x04 r 0x0 timecode_ready_signal_pluse_width //识别到一帧timecode信号后，输出一个脉冲信号，用于同步其他模块 - - parameter REG_TIMECODE_BIT_PERIOD_ADD = REG_START_ADD + 0; //timecode bit周期寄存器地址 - - - parameter ADD_NUM = 5; //寄存器数量 - parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 - reg [31:0] register[REG_START_ADD:REG_END_ADD]; - integer i; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - for (i = 0; i < ADD_NUM; i = i + 1) begin - register[i] <= 0; - end - end else begin - if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; - end - end - assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; - - - - // 416us 500us 520us - // 边沿触发--> 采样偏移同步 - // - - // 416us采用 160byte 采样到同步 - // 电平变化修正采样计数 - - // - // 配置: - // 1. 制式 - // 2. - - // 边沿信号捕获 - - - reg [160-1:0] tc_bit_2x; //timecode 每1/2bit - reg [79:0] tc_bit; //timecode 每1bit - reg sample_signal; //采样信号 - reg [31:0] sample_time_cnt; //采样计数 - wire sample_time_calibrate_signal; //采样信号修正器 - reg time_code_signal_edge; //timecode原始信号的边沿信号，即timecode上升沿或者下降沿时，置1 - assign timecode_signal_in_a = timecode_signal_in; // - reg timecode_signal_in_b; // - reg tc_sync_signal_edge; // timecode捕获到同步信号时，置1，此时可以解析timecode信号，并将其存放到寄存中 - - - /******************************************************************************* - * timecode边沿信号捕获 * - *******************************************************************************/ - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - timecode_signal_in_b <= 0; - end else begin - timecode_signal_in_b <= timecode_signal_in_a; - end - end - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - time_code_signal_edge <= 0; - end else begin - if (timecode_signal_in_a != timecode_signal_in_b) begin - time_code_signal_edge <= 1; - end else begin - time_code_signal_edge <= 0; - end - end - end - - assign sample_time_calibrate_signal = time_code_signal_edge; - - - /******************************************************************************* - * BIT信号映射 * - *******************************************************************************/ - // - // 采样点 采样点 采样点 采样点 - // + + + + - // ___------------_______-------- - // 0 1 - // timecode的每个bit要通过两个点进行判断，所以需要2x的采样率 - // - always @(*) begin - for (i = 0; i < 79; i = i + 1) begin - tc_bit[i] = !tc_bit_2x[i*2] & tc_bit_2x[i*2+1]; - end - end - - /******************************************************************************* - * 采样信号生成器 * - *******************************************************************************/ - // - // 1. 当捕获到timecode原始信号的边沿时，校准采样信号计数器 - // 2. 当采样信号计数器到达采样点时，输出采样信号 - // 3. 当采样信号计数器到达2倍采样点时，重置采样信号计数器 - // - assign timecode_sample_cnt_reset_signal = ( - sample_time_calibrate_signal|| - sample_time_cnt >= (register[REG_TIMECODE_BIT_PERIOD_ADD] << 1) - ); - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - sample_time_cnt <= 0; - sample_signal <= 0; - end else begin - if (timecode_sample_cnt_reset_signal) begin - sample_time_cnt <= 0; - sample_signal <= 0; - end else if (sample_time_cnt == register[REG_TIMECODE_BIT_PERIOD_ADD]) begin - sample_time_cnt <= sample_time_cnt + 1; - sample_signal <= 1; - end else begin - sample_time_cnt <= sample_time_cnt + 1; - sample_signal <= 0; - end - end - end - - // - // 根据sample_signal捕获timecode信号 - // - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - tc_bit_2x <= 0; - end else begin - if (sample_signal) begin - tc_bit_2x <= {tc_bit_2x[158:0], timecode_signal_in}; - end else begin - tc_bit_2x <= tc_bit_2x; - end - end - end - - /******************************************************************************* - * tc_sync_signal_edge * - *******************************************************************************/ - // ___------------_______-------- - // 0 1 - // - // 捕获timecode同步信号 - // - // 同步信号 - // 0011_1111_11111_1101 - // 1111_0101__0101_0101__0101_0101__0101_1101 - // - reg [31:0] sync_code_pattern = 32'b1111_0101__0101_0101__0101_0101__0101_1101; - assign tc_sync_signal = (tc_bit == sync_code_pattern); - reg tc_sync_signal_b; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - tc_sync_signal_b <= 0; - end else begin - tc_sync_signal_b <= tc_sync_signal; - - if (tc_sync_signal & !tc_sync_signal_b) begin - tc_sync_signal_edge <= 1; - end else begin - tc_sync_signal_edge <= 0; - end - end - end - - - - - assign timecode_freq_trigger_signal = tc_sync_signal_edge; - - - -endmodule +// module src_timecode_parser #( +// parameter REG_START_ADD = 0 +// ) ( +// input clk, //clock input +// input rst_n, //asynchronous reset input, low active + +// //regbus interface +// output reg [31:0] addr, +// input [31:0] wr_data, +// input wr_en, + +// inout wire [31:0] rd_data, //received serial data +// // 输入 +// input timecode_signal_in, +// //输出 +// output wire timecode_signal_orgin_output, //ttl原始数据 +// output wire timecode_freq_trigger_signal +// ); + +// /******************************************************************************* +// * 寄存器读写 * +// *******************************************************************************/ + +// // +// // @功能: +// // 1. 采样TIMECODE信号 +// // 2. 转发TIMECODE信号 +// // 3. TIMECODE信号成功解析 +// // 4. TIMECODE采样计数 +// // +// // @寄存器列表: +// // 地址 读写 默认 描述 +// // 0x00 wr 0x0 timecode bit周期 +// // 0x01 r 0x0 flag bit[0]:timecode_ready_flag +// // 0x02 r 0x0 timecode [31:0] +// // 0x03 r 0x0 timecode [63:32] +// // 0x04 r 0x0 timecode_ready_signal_pluse_width //识别到一帧timecode信号后，输出一个脉冲信号，用于同步其他模块 + +// parameter REG_TIMECODE_BIT_PERIOD_ADD = REG_START_ADD + 0; //timecode bit周期寄存器地址 + + +// parameter ADD_NUM = 5; //寄存器数量 +// parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 +// reg [31:0] register[REG_START_ADD:REG_END_ADD]; +// integer i; +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// for (i = 0; i < ADD_NUM; i = i + 1) begin +// register[i] <= 0; +// end +// end else begin +// if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; +// end +// end +// assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; + + + +// // 416us 500us 520us +// // 边沿触发--> 采样偏移同步 +// // + +// // 416us采用 160byte 采样到同步 +// // 电平变化修正采样计数 + +// // +// // 配置: +// // 1. 制式 +// // 2. + +// // 边沿信号捕获 + + +// reg [160-1:0] tc_bit_2x; //timecode 每1/2bit +// reg [79:0] tc_bit; //timecode 每1bit +// reg sample_signal; //采样信号 +// reg [31:0] sample_time_cnt; //采样计数 +// wire sample_time_calibrate_signal; //采样信号修正器 +// reg time_code_signal_edge; //timecode原始信号的边沿信号，即timecode上升沿或者下降沿时，置1 +// assign timecode_signal_in_a = timecode_signal_in; // +// reg timecode_signal_in_b; // +// reg tc_sync_signal_edge; // timecode捕获到同步信号时，置1，此时可以解析timecode信号，并将其存放到寄存中 + + +// /******************************************************************************* +// * timecode边沿信号捕获 * +// *******************************************************************************/ +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// timecode_signal_in_b <= 0; +// end else begin +// timecode_signal_in_b <= timecode_signal_in_a; +// end +// end + +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// time_code_signal_edge <= 0; +// end else begin +// if (timecode_signal_in_a != timecode_signal_in_b) begin +// time_code_signal_edge <= 1; +// end else begin +// time_code_signal_edge <= 0; +// end +// end +// end + +// assign sample_time_calibrate_signal = time_code_signal_edge; + + +// /******************************************************************************* +// * BIT信号映射 * +// *******************************************************************************/ +// // +// // 采样点 采样点 采样点 采样点 +// // + + + + +// // ___------------_______-------- +// // 0 1 +// // timecode的每个bit要通过两个点进行判断，所以需要2x的采样率 +// // +// always @(*) begin +// for (i = 0; i < 79; i = i + 1) begin +// tc_bit[i] = !tc_bit_2x[i*2] & tc_bit_2x[i*2+1]; +// end +// end + +// /******************************************************************************* +// * 采样信号生成器 * +// *******************************************************************************/ +// // +// // 1. 当捕获到timecode原始信号的边沿时，校准采样信号计数器 +// // 2. 当采样信号计数器到达采样点时，输出采样信号 +// // 3. 当采样信号计数器到达2倍采样点时，重置采样信号计数器 +// // +// assign timecode_sample_cnt_reset_signal = ( +// sample_time_calibrate_signal|| +// sample_time_cnt >= (register[REG_TIMECODE_BIT_PERIOD_ADD] << 1) +// ); +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// sample_time_cnt <= 0; +// sample_signal <= 0; +// end else begin +// if (timecode_sample_cnt_reset_signal) begin +// sample_time_cnt <= 0; +// sample_signal <= 0; +// end else if (sample_time_cnt == register[REG_TIMECODE_BIT_PERIOD_ADD]) begin +// sample_time_cnt <= sample_time_cnt + 1; +// sample_signal <= 1; +// end else begin +// sample_time_cnt <= sample_time_cnt + 1; +// sample_signal <= 0; +// end +// end +// end + +// // +// // 根据sample_signal捕获timecode信号 +// // +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// tc_bit_2x <= 0; +// end else begin +// if (sample_signal) begin +// tc_bit_2x <= {tc_bit_2x[158:0], timecode_signal_in}; +// end else begin +// tc_bit_2x <= tc_bit_2x; +// end +// end +// end + +// /******************************************************************************* +// * tc_sync_signal_edge * +// *******************************************************************************/ +// // ___------------_______-------- +// // 0 1 +// // +// // 捕获timecode同步信号 +// // +// // 同步信号 +// // 0011_1111_11111_1101 +// // 1111_0101__0101_0101__0101_0101__0101_1101 +// // +// reg [31:0] sync_code_pattern = 32'b1111_0101__0101_0101__0101_0101__0101_1101; +// assign tc_sync_signal = (tc_bit == sync_code_pattern); +// reg tc_sync_signal_b; +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// tc_sync_signal_b <= 0; +// end else begin +// tc_sync_signal_b <= tc_sync_signal; + +// if (tc_sync_signal & !tc_sync_signal_b) begin +// tc_sync_signal_edge <= 1; +// end else begin +// tc_sync_signal_edge <= 0; +// end +// end +// end + + + + +// assign timecode_freq_trigger_signal = tc_sync_signal_edge; + + + +// endmodule diff --git a/source/src/src_ttl_parser.v b/source/src/src_ttl_parser.v index cd767fc..b7b9a5b 100644 --- a/source/src/src_ttl_parser.v +++ b/source/src/src_ttl_parser.v @@ -1,131 +1,131 @@ -module src_ttl_parser #( - parameter REG_START_ADD = 0 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active +// module src_ttl_parser #( +// parameter REG_START_ADD = 0 +// ) ( +// input clk, //clock input +// input rst_n, //asynchronous reset input, low active - //regbus interface - output reg [31:0] addr, - input [31:0] wr_data, - input wr_en, +// //regbus interface +// output reg [31:0] addr, +// input [31:0] wr_data, +// input wr_en, - inout wire [31:0] rd_data, //received serial data - // 输入 - input ttlin, - //输出 - output wire ttl_output //ttl原始数据 -); - // - // @功能: - // 1. 计算ttl频率 - // 2. 转发ttl信号 - // 3. 分频倍频 - // - // @寄存器列表: - // 地址 读写 默认 描述 - // 0x00 r 0x0 function 0:原始信号输出 1:频率信号源 - // 0x01 r 0x0 freq //一个周期的计数，单位为 1/50M s - // 0x02 wr 0x0 pll_mul //暂不支持 - // 0x03 wr 0x0 pll_div - // 0x04 wr 0x0 [0]:信号源是上升沿触发，还是下降沿触发 - // +// inout wire [31:0] rd_data, //received serial data +// // 输入 +// input ttlin, +// //输出 +// output wire ttl_output //ttl原始数据 +// ); +// // +// // @功能: +// // 1. 计算ttl频率 +// // 2. 转发ttl信号 +// // 3. 分频倍频 +// // +// // @寄存器列表: +// // 地址 读写 默认 描述 +// // 0x00 r 0x0 function 0:原始信号输出 1:频率信号源 +// // 0x01 r 0x0 freq //一个周期的计数，单位为 1/50M s +// // 0x02 wr 0x0 pll_mul //暂不支持 +// // 0x03 wr 0x0 pll_div +// // 0x04 wr 0x0 [0]:信号源是上升沿触发，还是下降沿触发 +// // - reg ttl_origin_output; //ttl原始信号输出 - reg ttl_after_process_output; //ttl处理后信号输出 +// reg ttl_origin_output; //ttl原始信号输出 +// reg ttl_after_process_output; //ttl处理后信号输出 - /******************************************************************************* - * 寄存器读写 * - *******************************************************************************/ +// /******************************************************************************* +// * 寄存器读写 * +// *******************************************************************************/ - parameter ADD_NUM = 5; //寄存器数量 - parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 - reg [31:0] register[REG_START_ADD:REG_END_ADD]; - integer i; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - for (i = 0; i < ADD_NUM; i = i + 1) begin - register[i] <= 0; - end - end else begin - if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; - end - end - assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; +// parameter ADD_NUM = 5; //寄存器数量 +// parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 +// reg [31:0] register[REG_START_ADD:REG_END_ADD]; +// integer i; +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// for (i = 0; i < ADD_NUM; i = i + 1) begin +// register[i] <= 0; +// end +// end else begin +// if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; +// end +// end +// assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; - parameter REG_FUNC_ADD = REG_START_ADD + 0; - parameter REG_FREQ_ADD = REG_START_ADD + 1; - parameter REG_PLL_MUL_ADD = REG_START_ADD + 2; - parameter REG_PLL_DIV_ADD = REG_START_ADD + 3; - parameter REG_TTL_EDGE_ADD = REG_START_ADD + 4; +// parameter REG_FUNC_ADD = REG_START_ADD + 0; +// parameter REG_FREQ_ADD = REG_START_ADD + 1; +// parameter REG_PLL_MUL_ADD = REG_START_ADD + 2; +// parameter REG_PLL_DIV_ADD = REG_START_ADD + 3; +// parameter REG_TTL_EDGE_ADD = REG_START_ADD + 4; - /******************************************************************************* - * ttl输出路径选择 * - *******************************************************************************/ +// /******************************************************************************* +// * ttl输出路径选择 * +// *******************************************************************************/ - assign ttl_output = (register[REG_FUNC_ADD] == 0) ? ttl_origin_output : ttl_after_process_output; +// assign ttl_output = (register[REG_FUNC_ADD] == 0) ? ttl_origin_output : ttl_after_process_output; - /******************************************************************************* - * 原始信号输出 * - *******************************************************************************/ - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - ttl_origin_output <= 0; - end else begin - ttl_origin_output <= ttlin; - end - end +// /******************************************************************************* +// * 原始信号输出 * +// *******************************************************************************/ +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// ttl_origin_output <= 0; +// end else begin +// ttl_origin_output <= ttlin; +// end +// end - /******************************************************************************* - * ttl_in_last信号捕获 * - *******************************************************************************/ - reg ttl_in_last; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - ttl_in_last <= 0; - end else begin - ttl_in_last <= ttlin; - end - end +// /******************************************************************************* +// * ttl_in_last信号捕获 * +// *******************************************************************************/ +// reg ttl_in_last; +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// ttl_in_last <= 0; +// end else begin +// ttl_in_last <= ttlin; +// end +// end - /******************************************************************************* - * 频率探测 * - *******************************************************************************/ - reg [31:0] ttl_freq_cnt; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - ttl_freq_cnt <= 0; - end else begin - if (ttlin && !ttl_in_last) begin - register[REG_FREQ_ADD] <= ttl_freq_cnt; - ttl_freq_cnt <= 0; - end - if (ttl_freq_cnt != 32'hffff_ffff_ffff_ffff) begin - ttl_freq_cnt <= ttl_freq_cnt + 1; - end - end - end +// /******************************************************************************* +// * 频率探测 * +// *******************************************************************************/ +// reg [31:0] ttl_freq_cnt; +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// ttl_freq_cnt <= 0; +// end else begin +// if (ttlin && !ttl_in_last) begin +// register[REG_FREQ_ADD] <= ttl_freq_cnt; +// ttl_freq_cnt <= 0; +// end +// if (ttl_freq_cnt != 32'hffff_ffff_ffff_ffff) begin +// ttl_freq_cnt <= ttl_freq_cnt + 1; +// end +// end +// end - /******************************************************************************* - * 分频 * - *******************************************************************************/ - reg [31:0] ttl_in_cnt; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - ttl_in_cnt <= 0; - end else begin - if (ttlin && !ttl_in_last) begin - if (ttl_in_cnt <= register[REG_PLL_MUL_ADD]) begin - ttl_in_cnt <= ttl_in_cnt + 1; - end else begin - ttl_in_cnt <= 0; - ttl_after_process_output <= 1; - end - end else begin - ttl_after_process_output <= 0; - end - end - end -endmodule +// /******************************************************************************* +// * 分频 * +// *******************************************************************************/ +// reg [31:0] ttl_in_cnt; +// always @(posedge clk or negedge rst_n) begin +// if (!rst_n) begin +// ttl_in_cnt <= 0; +// end else begin +// if (ttlin && !ttl_in_last) begin +// if (ttl_in_cnt <= register[REG_PLL_MUL_ADD]) begin +// ttl_in_cnt <= ttl_in_cnt + 1; +// end else begin +// ttl_in_cnt <= 0; +// ttl_after_process_output <= 1; +// end +// end else begin +// ttl_after_process_output <= 0; +// end +// end +// end +// endmodule diff --git a/source/src/top.v b/source/src/top.v index c2670c8..6bbe488 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -1,8 +1,86 @@ +`include "config.v" `timescale 1ns / 1ns module Top ( input sys_clk, input rst_n, + /******************************************************************************* + * genlock * + *******************************************************************************/ + input genlock_in_hsync, + input genlock_in_vsync, + input genlock_in_fsync, + output genlock_state_led, + + /******************************************************************************* + * GENLOCK_OUTPUT * + *******************************************************************************/ + + output [12:0] genlock_out_dac, + output genlock_out_dac_state_led, + + /******************************************************************************* + * TTL_IN * + *******************************************************************************/ + + input sync_ttl_in1, + output sync_ttl_state_led1, + + input sync_ttl_in2, + output sync_ttl_state_led2, + + input sync_ttl_in3, + output sync_ttl_state_led3, + + input sync_ttl_in4, + output sync_ttl_state_led4, + + + /******************************************************************************* + * TTL_OUT * + *******************************************************************************/ + + input sync_ttl_out1, + output sync_ttl_out1_state_led, + + input sync_ttl_out2, + output sync_ttl_out2_state_led, + + input sync_ttl_out3, + output sync_ttl_out3_state_led, + + input sync_ttl_out4, + output sync_ttl_out4_state_led, + + /******************************************************************************* + * TIMECODE_IN * + *******************************************************************************/ + input timecode_headphone_in, + input timecode_headphone_in_state_led, + input timecode_bnc_in, + input timecode_bnc_in_state_led, + + /******************************************************************************* + * TIMECODE_OUTPUT * + *******************************************************************************/ + + output timecode_bnc_out, + output timecode_bnc_output_select, + output timecode_bnc_out_state_led, + + output timecode_headphone_out, + output timecode_headphone_output_select, + output timecode_headphone_out_state_led, + + /******************************************************************************* + * STM32_IF * + *******************************************************************************/ + output stm32if_camera_sync_out, + output stm32if_timecode_sync_out, + output stm32if_start_signal_out, + output [3:0] stm32if_timecode_add, + output [3:0] stm32if_timecode_data, + //SPI 串行总线1 input wire spi1_cs_pin, input wire spi1_clk_pin, @@ -15,9 +93,19 @@ module Top ( input wire spi2_rx_pin, output wire spi2_tx_pin, + /******************************************************************************* + * debug_signal_output * + *******************************************************************************/ + output [15:0] debug_signal_output, + + /******************************************************************************* + * CODE_BOARD * + *******************************************************************************/ output wire core_board_debug_led ); + localparam HARDWARE_TEST_MODE = 1; + SPLL spll ( .clkin1(sys_clk), // input .pll_lock(pll_lock), // output @@ -90,24 +178,78 @@ module Top ( .spi_tx_pin(spi1_tx_pin) ); + + rd_data_router rd_data_router_inst ( + .addr(reg_reader_bus_addr), + + .stm32_rd_data(stm32_if_rd_data), + .fpga_test_rd_data(fpga_test_rd_data), + .control_sensor_rd_data(control_sensor_rd_data), + .ttlin1_rd_data(ttlin1_rd_data), + .ttlin2_rd_data(ttlin2_rd_data), + .ttlin3_rd_data(ttlin3_rd_data), + .ttlin4_rd_data(ttlin4_rd_data), + .timecode_in_rd_data(timecode_in_rd_data), + .genlock_in_rd_data(genlock_in_rd_data), + .ttlout1_rd_data(ttlout1_rd_data), + .ttlout2_rd_data(ttlout2_rd_data), + .ttlout3_rd_data(ttlout3_rd_data), + .ttlout4_rd_data(ttlout4_rd_data), + .timecode_out_rd_data(timecode_out_rd_data), + .genlock_out_rd_data(genlock_out_rd_data), + .stm32_if_rd_data(stm32_if_rd_data), + .debuger_rd_data(debuger_rd_data), + + .rd_data_out(reg_reader_bus_rd_data) + ); + + /******************************************************************************* * TEST_SPI_REG * *******************************************************************************/ zutils_register16 #( - .REG_START_ADD(16'h0020) + .REG_START_ADD(`REG_ADD_OFF_FPGA_TEST) ) core_board_debug_led_reg ( .clk(sys_clk), .rst_n(rst_n), .addr(reg_reader_bus_addr), .wr_data(reg_reader_bus_wr_data), .wr_en(reg_reader_bus_wr_en), - .rd_data(reg_reader_bus_rd_data) + .rd_data(fpga_test_rd_data) ); -// assign trig0_i[0] = sys_clk_5m; -// assign trig0_i[1] = spi2_clk_pin; -// assign trig0_i[2] = spi1_rx_pin; -// assign trig0_i[3] = spi1_tx_pin; -// assign trig0_i[4] = spi1_cs_pin; + + /******************************************************************************* + * 输出组件 * + *******************************************************************************/ + + wire [7:0] ttl_output_trigger_signal_src; + genvar i; + + wire sync_ttl_out[0:3] = {sync_ttl_out1,sync_ttl_out2,sync_ttl_out3,sync_ttl_out4}; + wire sync_ttl_out_state_led[0:3] = {sync_ttl_out1_state_led,sync_ttl_out2_state_led,sync_ttl_out3_state_led,sync_ttl_out4_state_led}; + wire [31:0]ttloutx_rd_data [0:3] = {ttlout1_rd_data,ttlout2_rd_data,ttlout3_rd_data,ttlout4_rd_data}; + + generate + for (i = 0; i < 4; i = i + 1) begin + ttl_output #( + .REG_START_ADD(`REG_ADD_OFF_TTLIN1+i*16), + .TEST(HARDWARE_TEST_MODE) + ) ttl_output_1 ( + .clk (sys_clk), + .rst_n(rst_n), + + .addr(reg_reader_bus_addr), + .wr_data(reg_reader_bus_wr_data), + .wr_en(reg_reader_bus_wr_en), + .rd_data(ttloutx_rd_data[i]), + + .signal_in(ttl_output_trigger_signal_src), + + .ttloutput(sync_ttl_out[i]), + .ttloutput_state_led(sync_ttl_out_state_led[i]) + ); + end + endgenerate endmodule diff --git a/source/src/zutils/zutils_multiplexer_16t1.v b/source/src/zutils/zutils_multiplexer_16t1.v new file mode 100644 index 0000000..9c03531 --- /dev/null +++ b/source/src/zutils/zutils_multiplexer_16t1.v @@ -0,0 +1,64 @@ +module zutils_multiplexer_16t1 ( + input [31:0] chooseindex, + input wire [15:0] signal, + output reg signalout +); + + always @(*) begin + case (chooseindex) + 0: begin + signalout = signal[0]; + end + 1: begin + signalout = signal[1]; + end + 2: begin + signalout = signal[2]; + end + 3: begin + signalout = signal[3]; + end + 4: begin + signalout = signal[4]; + end + 5: begin + signalout = signal[5]; + end + 6: begin + signalout = signal[6]; + end + 7: begin + signalout = signal[7]; + end + 8: begin + signalout = signal[8]; + end + 9: begin + signalout = signal[9]; + end + 10: begin + signalout = signal[10]; + end + 11: begin + signalout = signal[11]; + end + 12: begin + signalout = signal[12]; + end + 13: begin + signalout = signal[13]; + end + 14: begin + signalout = signal[14]; + end + 15: begin + signalout = signal[15]; + end + default: begin + signalout = 0; + end + endcase + end + + +endmodule diff --git a/source/src/zutils/zutils_pwm_generator.v b/source/src/zutils/zutils_pwm_generator.v new file mode 100644 index 0000000..86c00ff --- /dev/null +++ b/source/src/zutils/zutils_pwm_generator.v @@ -0,0 +1,28 @@ +module zutils_pwm_generator #( + parameter SYS_CLOCK_FREQ = 50000000, + parameter OUTPUT_FREQ = 1000 +) ( + input clk, + input rst_n, + output reg output_signal + +); + + localparam COUNT = SYS_CLOCK_FREQ / OUTPUT_FREQ; + reg [31:0] counter = 0; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + counter <= 0; + output_signal <= 0; + end else begin + if (counter == 0) begin + counter <= COUNT - 1; + output_signal <= 1; + end else begin + counter <= counter - 1; + output_signal <= 0; + end + end + end +endmodule diff --git a/source/src/zutils/zutils_register.v b/source/src/zutils/zutils_register.v index 9e67957..28bc564 100644 --- a/source/src/zutils/zutils_register.v +++ b/source/src/zutils/zutils_register.v @@ -1,5 +1,22 @@ module zutils_register16 #( - parameter REG_START_ADD = 0 + parameter REG_START_ADD = 0, + parameter REG0_INIT = 0, + parameter REG1_INIT = 0, + parameter REG2_INIT = 0, + parameter REG3_INIT = 0, + parameter REG4_INIT = 0, + parameter REG5_INIT = 0, + parameter REG6_INIT = 0, + parameter REG7_INIT = 0, + parameter REG8_INIT = 0, + parameter REG9_INIT = 0, + parameter REGA_INIT = 0, + parameter REGB_INIT = 0, + parameter REGC_INIT = 0, + parameter REGD_INIT = 0, + parameter REGE_INIT = 0, + parameter REGF_INIT = 0 + ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active @@ -9,7 +26,7 @@ module zutils_register16 #( input [31:0] wr_data, input wr_en, - inout wire [31:0] rd_data, //received serial data + output [31:0] rd_data, //received serial data output [31:0] reg0, output [31:0] reg1, @@ -33,7 +50,6 @@ module zutils_register16 #( parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 reg [31:0] data[0:ADD_NUM]; - assign reg0 = data[0]; assign reg1 = data[1]; assign reg2 = data[2]; @@ -54,15 +70,28 @@ module zutils_register16 #( integer i; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - for (i = 0; i < ADD_NUM; i = i + 1) begin - data[i] <= 0; - end + data[0] <= REG0_INIT; + data[1] <= REG1_INIT; + data[2] <= REG2_INIT; + data[3] <= REG3_INIT; + data[4] <= REG4_INIT; + data[5] <= REG5_INIT; + data[6] <= REG6_INIT; + data[7] <= REG7_INIT; + data[8] <= REG8_INIT; + data[9] <= REG9_INIT; + data[10] <= REGA_INIT; + data[11] <= REGB_INIT; + data[12] <= REGC_INIT; + data[13] <= REGD_INIT; + data[14] <= REGE_INIT; + data[15] <= REGF_INIT; end else begin if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) data[addr-REG_START_ADD] <= wr_data; end end - assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr-REG_START_ADD] : 31'bz; + assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr-REG_START_ADD] : 31'b0; endmodule