From 12d4a4834b98cacd93589af8ebf9a06fe4d0c301 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Mon, 8 Jan 2024 18:12:43 +0800 Subject: [PATCH] update --- led_test.fdc | 56 +++++--- led_test.pds | 78 +++++------ source/src/rd_data_router.v | 4 +- source/src/spi_reg_reader.v | 20 +-- source/src/top.v | 202 ++++++++++++++-------------- source/src/zutils/zutils_edge_detecter.v | 18 +-- source/src/zutils/zutils_multiplexer_16t1.v | 4 +- source/src/zutils/zutils_multiplexer_4t1.v | 4 +- source/src/zutils/zutils_pluse_generator.v | 4 +- source/src/zutils/zutils_pwm_generator.v | 9 +- source/src/zutils/zutils_register.v | 2 +- source/src/zutils/zutils_register.v.bak | 96 +++++++++++++ source/src/zutils/zutils_signal_filter.v | 4 +- source/test/test_top.v | 40 +++--- 14 files changed, 331 insertions(+), 210 deletions(-) create mode 100644 source/src/zutils/zutils_register.v.bak diff --git a/led_test.fdc b/led_test.fdc index f805e77..fb646cc 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -345,24 +345,44 @@ define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_VCCIO} {3.3} define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DRIVE} {4} define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {P17} -define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {L12} -define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {R18} -define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {R17} -define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} -define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {P17} +# define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {L12} +# define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {R18} +# define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {R17} +# define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} +# define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} + +# define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {U13} +# define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} +# define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V13} +# define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {V14} +# define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {U14} +# define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} + define_attribute {p:spi2_cs_pin} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:spi2_cs_pin} {PAP_IO_LOC} {V14} define_attribute {p:spi2_cs_pin} {PAP_IO_VCCIO} {3.3} diff --git a/led_test.pds b/led_test.pds index 0a4bb1b..8de43e4 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 17:16:47 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 18:12:27 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,27 +19,27 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-08T17:16:22") + (_timespec "2024-01-08T18:10:14") ) (_file "source/src/spi_reg_reader.v" (_format verilog) - (_timespec "2024-01-08T17:03:05") + (_timespec "2024-01-08T17:40:40") ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) - (_timespec "2024-01-08T16:56:59") + (_timespec "2024-01-08T17:43:24") ) (_file "source/src/zutils/zutils_edge_detecter.v" (_format verilog) - (_timespec "2024-01-08T16:56:16") + (_timespec "2024-01-08T17:41:58") ) (_file "source/src/zutils/zutils_register.v" (_format verilog) - (_timespec "2024-01-08T16:58:13") + (_timespec "2024-01-08T18:05:38") ) (_file "source/src/zutils/zutils_multiplexer_4t1.v" (_format verilog) - (_timespec "2024-01-08T16:56:29") + (_timespec "2024-01-08T17:42:11") ) (_file "source/src/zutils/zutils_debug_led.v" (_format verilog) @@ -47,7 +47,7 @@ ) (_file "source/src/zutils/zutils_signal_filter.v" (_format verilog) - (_timespec "2024-01-08T16:58:37") + (_timespec "2024-01-08T17:44:10") ) (_file "source/src/zutils/zutils_clk_parser.v" (_format verilog) @@ -55,7 +55,7 @@ ) (_file "source/src/zutils/zutils_multiplexer_16t1.v" (_format verilog) - (_timespec "2024-01-08T16:56:42") + (_timespec "2024-01-08T17:42:43") ) (_file "source/src/output/ttl_output.v" (_format verilog) @@ -63,11 +63,11 @@ ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) - (_timespec "2024-01-08T16:57:17") + (_timespec "2024-01-08T17:43:42") ) (_file "source/src/rd_data_router.v" (_format verilog) - (_timespec "2024-01-08T17:01:42") + (_timespec "2024-01-08T17:44:45") ) ) ) @@ -85,7 +85,7 @@ (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2024-01-08T16:54:45") + (_timespec "2024-01-08T18:10:50") ) ) ) @@ -109,7 +109,7 @@ ) (_file "source/test/test_top.v" + "test_top:" (_format verilog) - (_timespec "2024-01-07T19:04:55") + (_timespec "2024-01-08T18:12:26") ) (_file "source/test/test_uart_reg_reader.v" (_format verilog) @@ -128,17 +128,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-08T17:16:26") + (_timespec "2024-01-08T18:10:54") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-08T17:16:25") + (_timespec "2024-01-08T18:10:54") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-08T17:16:26") + (_timespec "2024-01-08T18:10:54") ) ) ) @@ -154,21 +154,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-01-08T17:16:29") + (_timespec "2024-01-08T18:10:57") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-01-08T17:16:29") + (_timespec "2024-01-08T18:10:57") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-01-08T17:16:29") + (_timespec "2024-01-08T18:10:58") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-08T17:16:29") + (_timespec "2024-01-08T18:10:58") ) ) ) @@ -189,21 +189,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-01-08T17:16:32") + (_timespec "2024-01-08T18:11:00") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-01-08T17:16:32") + (_timespec "2024-01-08T18:11:00") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-01-08T17:16:32") + (_timespec "2024-01-08T18:11:00") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-01-08T17:16:32") + (_timespec "2024-01-08T18:11:00") ) ) ) @@ -212,7 +212,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-08T17:16:32") + (_timespec "2024-01-08T18:11:00") ) ) ) @@ -226,33 +226,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-01-08T17:16:38") + (_timespec "2024-01-08T18:11:08") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-01-08T17:16:38") + (_timespec "2024-01-08T18:11:08") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-01-08T17:16:38") + (_timespec "2024-01-08T18:11:08") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-01-08T17:16:38") + (_timespec "2024-01-08T18:11:08") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-01-08T17:16:36") + (_timespec "2024-01-08T18:11:05") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-01-08T17:16:38") + (_timespec "2024-01-08T18:11:08") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-01-08T17:16:38") + (_timespec "2024-01-08T18:11:08") ) ) ) @@ -268,17 +268,17 @@ (_db_output (_file "report_timing/Top_rtp.adf" (_format adif) - (_timespec "2024-01-08T17:16:41") + (_timespec "2024-01-08T18:11:11") ) ) (_output (_file "report_timing/Top.rtr" (_format text) - (_timespec "2024-01-08T17:16:41") + (_timespec "2024-01-08T18:11:11") ) (_file "report_timing/rtr.db" (_format text) - (_timespec "2024-01-08T17:16:42") + (_timespec "2024-01-08T18:11:12") ) ) ) @@ -302,19 +302,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-01-08T17:16:47") + (_timespec "2024-01-08T18:11:17") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-01-08T17:16:47") + (_timespec "2024-01-08T18:11:17") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-01-08T17:16:47") + (_timespec "2024-01-08T18:11:17") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-01-08T17:16:47") + (_timespec "2024-01-08T18:11:17") ) ) ) diff --git a/source/src/rd_data_router.v b/source/src/rd_data_router.v index 87c8367..552ce54 100644 --- a/source/src/rd_data_router.v +++ b/source/src/rd_data_router.v @@ -24,10 +24,10 @@ module rd_data_router ( input [31:0] stm32_if_rd_data, input [31:0] debuger_rd_data, - output [31:0] rd_data_out + output reg [31:0] rd_data_out ); - reg [31:0] rd_data_out = 0; + initial rd_data_out = 0; always @(*) begin case (addr >> 8) diff --git a/source/src/spi_reg_reader.v b/source/src/spi_reg_reader.v index 13ce26f..e2fc310 100644 --- a/source/src/spi_reg_reader.v +++ b/source/src/spi_reg_reader.v @@ -3,15 +3,15 @@ module spi_reg_reader ( input rst_n, //asynchronous reset input, low active //regbus interface - output [31:0] addr, - output [31:0] wr_data, - output wr_en, + output reg [31:0] addr, + output reg [31:0] wr_data, + output reg wr_en, input wire [31:0] rd_data, //received serial data // input wire spi_cs_pin, // input wire spi_clk_pin, // input wire spi_rx_pin, // - output spi_tx_pin + output reg spi_tx_pin ); parameter STATE_IDLE = 0; @@ -22,10 +22,12 @@ module spi_reg_reader ( parameter STATE_WRITE_REG = 5; parameter ADDRESS_WIDTH_BYTE_NUM = 2; - reg [31:0] addr = 0; - reg [31:0] wr_data = 0; - reg wr_en = 0; - reg spi_tx_pin = 0; + initial begin + addr = 0; + wr_data = 0; + wr_en = 0; + spi_tx_pin = 0; + end zutils_signal_filter #( @@ -150,7 +152,7 @@ module spi_reg_reader ( /******************************************************************************* * 缓存接收到的数据 * *******************************************************************************/ - reg [7:0] spi_rx_data_cache[0:7] = 0; + reg [7:0] spi_rx_data_cache[0:7]; genvar i; always @(posedge clk or negedge rst_n) begin if (!rst_n || spi_cs_pin_after_filter) begin diff --git a/source/src/top.v b/source/src/top.v index 05eb5ee..ee4908d 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -173,50 +173,50 @@ module Top ( .wr_en(reg_reader_bus_wr_en), .rd_data(reg_reader_bus_rd_data), // - .spi_cs_pin(spi1_cs_pin), - .spi_clk_pin(spi1_clk_pin), - .spi_rx_pin(spi1_rx_pin), - .spi_tx_pin(spi1_tx_pin) + .spi_cs_pin(spi2_cs_pin), + .spi_clk_pin(spi2_clk_pin), + .spi_rx_pin(spi2_rx_pin), + .spi_tx_pin(spi2_tx_pin) ); - rd_data_router rd_data_router_inst ( - .addr(reg_reader_bus_addr), +// rd_data_router rd_data_router_inst ( +// .addr(reg_reader_bus_addr), - .stm32_rd_data(0), - .fpga_test_rd_data(fpga_test_rd_data), - .control_sensor_rd_data(control_sensor_rd_data), - .ttlin1_rd_data(ttlin1_rd_data), - .ttlin2_rd_data(ttlin2_rd_data), - .ttlin3_rd_data(ttlin3_rd_data), - .ttlin4_rd_data(ttlin4_rd_data), - .timecode_in_rd_data(timecode_in_rd_data), - .genlock_in_rd_data(genlock_in_rd_data), - .ttlout1_rd_data(ttlout1_rd_data), // ok - .ttlout2_rd_data(ttlout2_rd_data), // ok - .ttlout3_rd_data(ttlout3_rd_data), // ok - .ttlout4_rd_data(ttlout4_rd_data), // ok - .timecode_out_rd_data(timecode_out_rd_data), - .genlock_out_rd_data(genlock_out_rd_data), - .stm32_if_rd_data(stm32_if_rd_data), - .debuger_rd_data(debuger_rd_data), - - .rd_data_out(reg_reader_bus_rd_data) - ); +// .stm32_rd_data(0), +// .fpga_test_rd_data(fpga_test_rd_data), +// .control_sensor_rd_data(control_sensor_rd_data), +// .ttlin1_rd_data(ttlin1_rd_data), +// .ttlin2_rd_data(ttlin2_rd_data), +// .ttlin3_rd_data(ttlin3_rd_data), +// .ttlin4_rd_data(ttlin4_rd_data), +// .timecode_in_rd_data(timecode_in_rd_data), +// .genlock_in_rd_data(genlock_in_rd_data), +// .ttlout1_rd_data(ttlout1_rd_data), // ok +// .ttlout2_rd_data(ttlout2_rd_data), // ok +// .ttlout3_rd_data(ttlout3_rd_data), // ok +// .ttlout4_rd_data(ttlout4_rd_data), // ok +// .timecode_out_rd_data(timecode_out_rd_data), +// .genlock_out_rd_data(genlock_out_rd_data), +// .stm32_if_rd_data(stm32_if_rd_data), +// .debuger_rd_data(debuger_rd_data), + +// .rd_data_out(reg_reader_bus_rd_data) +// ); /******************************************************************************* * TEST_SPI_REG * *******************************************************************************/ zutils_register16 #( - .REG_START_ADD(`REG_ADD_OFF_FPGA_TEST) + .REG_START_ADD(16'h00020) ) core_board_debug_led_reg ( .clk(sys_clk), .rst_n(rst_n), .addr(reg_reader_bus_addr), .wr_data(reg_reader_bus_wr_data), .wr_en(reg_reader_bus_wr_en), - .rd_data(fpga_test_rd_data) + .rd_data(reg_reader_bus_rd_data) ); @@ -224,79 +224,79 @@ module Top ( * 输出组件 * *******************************************************************************/ - wire [7:0] ttl_output_signal_in; - - ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLIN1), - .TEST(HARDWARE_TEST_MODE) - ) ttl_output_1 ( - .clk (sys_clk), - .rst_n(rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout1_rd_data), - - .signal_in(ttl_output_signal_in), - - .ttloutput(sync_ttl_out1), - .ttloutput_state_led(sync_ttl_out1_state_led) - ); - - ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLIN2), - .TEST(HARDWARE_TEST_MODE) - ) ttl_output_2 ( - .clk (sys_clk), - .rst_n(rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout2_rd_data), - - .signal_in(ttl_output_signal_in), - - .ttloutput(sync_ttl_out2), - .ttloutput_state_led(sync_ttl_out2_state_led) - ); - - ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLIN3), - .TEST(HARDWARE_TEST_MODE) - ) ttl_output_3 ( - .clk (sys_clk), - .rst_n(rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout3_rd_data), - - .signal_in(ttl_output_signal_in), - - .ttloutput(sync_ttl_out3), - .ttloutput_state_led(sync_ttl_out3_state_led) - ); - - ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLIN4), - .TEST(HARDWARE_TEST_MODE) - ) ttl_output_4 ( - .clk (sys_clk), - .rst_n(rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout4_rd_data), - - .signal_in(ttl_output_signal_in), - - .ttloutput(sync_ttl_out4), - .ttloutput_state_led(sync_ttl_out4_state_led) - ); +// wire [7:0] ttl_output_signal_in; + +// ttl_output #( +// .REG_START_ADD(`REG_ADD_OFF_TTLIN1), +// .TEST(HARDWARE_TEST_MODE) +// ) ttl_output_1 ( +// .clk (sys_clk), +// .rst_n(rst_n), + +// .addr(reg_reader_bus_addr), +// .wr_data(reg_reader_bus_wr_data), +// .wr_en(reg_reader_bus_wr_en), +// .rd_data(ttlout1_rd_data), + +// .signal_in(ttl_output_signal_in), + +// .ttloutput(sync_ttl_out1), +// .ttloutput_state_led(sync_ttl_out1_state_led) +// ); + +// ttl_output #( +// .REG_START_ADD(`REG_ADD_OFF_TTLIN2), +// .TEST(HARDWARE_TEST_MODE) +// ) ttl_output_2 ( +// .clk (sys_clk), +// .rst_n(rst_n), + +// .addr(reg_reader_bus_addr), +// .wr_data(reg_reader_bus_wr_data), +// .wr_en(reg_reader_bus_wr_en), +// .rd_data(ttlout2_rd_data), + +// .signal_in(ttl_output_signal_in), + +// .ttloutput(sync_ttl_out2), +// .ttloutput_state_led(sync_ttl_out2_state_led) +// ); + +// ttl_output #( +// .REG_START_ADD(`REG_ADD_OFF_TTLIN3), +// .TEST(HARDWARE_TEST_MODE) +// ) ttl_output_3 ( +// .clk (sys_clk), +// .rst_n(rst_n), + +// .addr(reg_reader_bus_addr), +// .wr_data(reg_reader_bus_wr_data), +// .wr_en(reg_reader_bus_wr_en), +// .rd_data(ttlout3_rd_data), + +// .signal_in(ttl_output_signal_in), + +// .ttloutput(sync_ttl_out3), +// .ttloutput_state_led(sync_ttl_out3_state_led) +// ); + +// ttl_output #( +// .REG_START_ADD(`REG_ADD_OFF_TTLIN4), +// .TEST(HARDWARE_TEST_MODE) +// ) ttl_output_4 ( +// .clk (sys_clk), +// .rst_n(rst_n), + +// .addr(reg_reader_bus_addr), +// .wr_data(reg_reader_bus_wr_data), +// .wr_en(reg_reader_bus_wr_en), +// .rd_data(ttlout4_rd_data), + +// .signal_in(ttl_output_signal_in), + +// .ttloutput(sync_ttl_out4), +// .ttloutput_state_led(sync_ttl_out4_state_led) +// ); endmodule diff --git a/source/src/zutils/zutils_edge_detecter.v b/source/src/zutils/zutils_edge_detecter.v index 14c8d9a..3e7bbbf 100644 --- a/source/src/zutils/zutils_edge_detecter.v +++ b/source/src/zutils/zutils_edge_detecter.v @@ -2,16 +2,18 @@ module zutils_edge_detecter ( input clk, //clock input input rst_n, //asynchronous reset input, low active input wire in_signal, - output in_signal_last, - output in_signal_rising_edge, - output in_signal_falling_edge, - output in_signal_edge + output reg in_signal_last, + output reg in_signal_rising_edge, + output reg in_signal_falling_edge, + output reg in_signal_edge ); - reg in_signal_last = 0; - reg in_signal_rising_edge = 0; - reg in_signal_falling_edge = 0; - reg in_signal_edge = 0; + initial begin + in_signal_last = 0; + in_signal_rising_edge = 0; + in_signal_falling_edge = 0; + in_signal_edge = 0; + end diff --git a/source/src/zutils/zutils_multiplexer_16t1.v b/source/src/zutils/zutils_multiplexer_16t1.v index 4613fc3..21d4e18 100644 --- a/source/src/zutils/zutils_multiplexer_16t1.v +++ b/source/src/zutils/zutils_multiplexer_16t1.v @@ -1,10 +1,10 @@ module zutils_multiplexer_16t1 ( input [31:0] chooseindex, input wire [15:0] signal, - output signalout + output reg signalout ); - reg signalout = 0; + initial signalout = 0; always @(*) begin case (chooseindex) diff --git a/source/src/zutils/zutils_multiplexer_4t1.v b/source/src/zutils/zutils_multiplexer_4t1.v index 836dcf0..49ad3e3 100644 --- a/source/src/zutils/zutils_multiplexer_4t1.v +++ b/source/src/zutils/zutils_multiplexer_4t1.v @@ -4,10 +4,10 @@ module zutils_multiplexer_4t1 ( input wire signal1, input wire signal2, input wire signal3, - output signalout + output reg signalout ); - reg signalout = 0; + initial signalout = 0; always @(*) begin case (chooseindex) diff --git a/source/src/zutils/zutils_pluse_generator.v b/source/src/zutils/zutils_pluse_generator.v index 0d2f81d..657c88a 100644 --- a/source/src/zutils/zutils_pluse_generator.v +++ b/source/src/zutils/zutils_pluse_generator.v @@ -4,11 +4,11 @@ module zutils_pluse_generator ( input wire [31:0] pluse_width, input wire trigger, - output output_signal + output reg output_signal ); - reg output_signal = 0; + initial output_signal = 0; reg [31:0] counter = 0; always @(posedge clk or negedge rst_n) begin diff --git a/source/src/zutils/zutils_pwm_generator.v b/source/src/zutils/zutils_pwm_generator.v index cc6efae..d55efb5 100644 --- a/source/src/zutils/zutils_pwm_generator.v +++ b/source/src/zutils/zutils_pwm_generator.v @@ -2,15 +2,16 @@ module zutils_pwm_generator #( parameter SYS_CLOCK_FREQ = 50000000, parameter OUTPUT_FREQ = 1000 ) ( - input clk, - input rst_n, - output output_signal + input clk, + input rst_n, + output reg output_signal ); + initial output_signal = 0; + localparam COUNT = SYS_CLOCK_FREQ / OUTPUT_FREQ; reg [31:0] counter = 0; - reg output_signal = 0; always @(posedge clk or negedge rst_n) begin diff --git a/source/src/zutils/zutils_register.v b/source/src/zutils/zutils_register.v index 57f56d6..22301e5 100644 --- a/source/src/zutils/zutils_register.v +++ b/source/src/zutils/zutils_register.v @@ -47,7 +47,7 @@ module zutils_register16 #( ); parameter REG_END_ADD = REG_START_ADD + 16 - 1; //寄存器结束地址 - reg [31:0] data[0:15] = 0; + reg [31:0] data[0:15]; assign reg0 = data[0]; assign reg1 = data[1]; diff --git a/source/src/zutils/zutils_register.v.bak b/source/src/zutils/zutils_register.v.bak new file mode 100644 index 0000000..57f56d6 --- /dev/null +++ b/source/src/zutils/zutils_register.v.bak @@ -0,0 +1,96 @@ +module zutils_register16 #( + parameter REG_START_ADD = 0, + parameter REG0_INIT = 0, + parameter REG1_INIT = 0, + parameter REG2_INIT = 0, + parameter REG3_INIT = 0, + parameter REG4_INIT = 0, + parameter REG5_INIT = 0, + parameter REG6_INIT = 0, + parameter REG7_INIT = 0, + parameter REG8_INIT = 0, + parameter REG9_INIT = 0, + parameter REGA_INIT = 0, + parameter REGB_INIT = 0, + parameter REGC_INIT = 0, + parameter REGD_INIT = 0, + parameter REGE_INIT = 0, + parameter REGF_INIT = 0 + +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //regbus interface + input [31:0] addr, + input [31:0] wr_data, + input wr_en, + + output [31:0] rd_data, //received serial data + + output [31:0] reg0, + output [31:0] reg1, + output [31:0] reg2, + output [31:0] reg3, + output [31:0] reg4, + output [31:0] reg5, + output [31:0] reg6, + output [31:0] reg7, + output [31:0] reg8, + output [31:0] reg9, + output [31:0] regA, + output [31:0] regB, + output [31:0] regC, + output [31:0] regD, + output [31:0] regE, + output [31:0] regF +); + + parameter REG_END_ADD = REG_START_ADD + 16 - 1; //寄存器结束地址 + reg [31:0] data[0:15] = 0; + + assign reg0 = data[0]; + assign reg1 = data[1]; + assign reg2 = data[2]; + assign reg3 = data[3]; + assign reg4 = data[4]; + assign reg5 = data[5]; + assign reg6 = data[6]; + assign reg7 = data[7]; + assign reg8 = data[8]; + assign reg9 = data[9]; + assign regA = data[10]; + assign regB = data[11]; + assign regC = data[12]; + assign regD = data[13]; + assign regE = data[14]; + assign regF = data[15]; + + integer i; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + data[0] <= REG0_INIT; + data[1] <= REG1_INIT; + data[2] <= REG2_INIT; + data[3] <= REG3_INIT; + data[4] <= REG4_INIT; + data[5] <= REG5_INIT; + data[6] <= REG6_INIT; + data[7] <= REG7_INIT; + data[8] <= REG8_INIT; + data[9] <= REG9_INIT; + data[10] <= REGA_INIT; + data[11] <= REGB_INIT; + data[12] <= REGC_INIT; + data[13] <= REGD_INIT; + data[14] <= REGE_INIT; + data[15] <= REGF_INIT; + end else begin + if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) + data[addr-REG_START_ADD] <= wr_data; + end + end + assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr-REG_START_ADD] : 31'b0; + + +endmodule diff --git a/source/src/zutils/zutils_signal_filter.v b/source/src/zutils/zutils_signal_filter.v index 4fa4771..859fa5f 100644 --- a/source/src/zutils/zutils_signal_filter.v +++ b/source/src/zutils/zutils_signal_filter.v @@ -4,9 +4,9 @@ module zutils_signal_filter #( input clk, //clock input input rst_n, //asynchronous reset input, low active input wire in, - output out + output reg out ); - reg out = 0; + initial out = 0; reg [31:0] counter = 0; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin diff --git a/source/test/test_top.v b/source/test/test_top.v index b8a8f10..78c40a6 100644 --- a/source/test/test_top.v +++ b/source/test/test_top.v @@ -5,15 +5,15 @@ module test_top; wire core_board_debug_led; - reg spi1_cs_pin; - reg spi1_clk_pin; - reg spi1_tx_pin; - wire spi1_rx_pin; + reg spi2_cs_pin; + reg spi2_clk_pin; + reg spi2_tx_pin; + wire spi2_rx_pin; initial begin - spi1_cs_pin = 1; - spi1_clk_pin = 1; - spi1_tx_pin = 1; + spi2_cs_pin = 1; + spi2_clk_pin = 1; + spi2_tx_pin = 1; end @@ -23,24 +23,24 @@ module test_top; integer i; begin addr[15] = 1; - spi1_cs_pin = 0; + spi2_cs_pin = 0; #30; // 100ns for (i = 0; i < 48; i = i + 1) begin - spi1_clk_pin = 0; - if (i <= 15) spi1_tx_pin = addr[i]; - else spi1_tx_pin = data[i-16]; + spi2_clk_pin = 0; + if (i <= 15) spi2_tx_pin = addr[i]; + else spi2_tx_pin = data[i-16]; #30; - spi1_clk_pin = 1; + spi2_clk_pin = 1; #30; end - spi1_clk_pin = 0; + spi2_clk_pin = 0; #10; - spi1_clk_pin = 1; + spi2_clk_pin = 1; #20; - spi1_cs_pin = 1; - spi1_tx_pin = 1; + spi2_cs_pin = 1; + spi2_tx_pin = 1; #300; end endtask @@ -51,10 +51,10 @@ module test_top; .rst_n(rst_n), .core_board_debug_led(core_board_debug_led), - .spi1_cs_pin (spi1_cs_pin), - .spi1_clk_pin(spi1_clk_pin), - .spi1_rx_pin (spi1_tx_pin), - .spi1_tx_pin (spi1_rx_pin) + .spi2_cs_pin (spi2_cs_pin), + .spi2_clk_pin(spi2_clk_pin), + .spi2_rx_pin (spi2_tx_pin), + .spi2_tx_pin (spi2_rx_pin) );