14 changed files with 331 additions and 210 deletions
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56led_test.fdc
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78led_test.pds
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4source/src/rd_data_router.v
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20source/src/spi_reg_reader.v
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172source/src/top.v
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18source/src/zutils/zutils_edge_detecter.v
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4source/src/zutils/zutils_multiplexer_16t1.v
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4source/src/zutils/zutils_multiplexer_4t1.v
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4source/src/zutils/zutils_pluse_generator.v
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5source/src/zutils/zutils_pwm_generator.v
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2source/src/zutils/zutils_register.v
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96source/src/zutils/zutils_register.v.bak
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4source/src/zutils/zutils_signal_filter.v
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40source/test/test_top.v
@ -0,0 +1,96 @@ |
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module zutils_register16 #( |
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parameter REG_START_ADD = 0, |
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parameter REG0_INIT = 0, |
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parameter REG1_INIT = 0, |
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parameter REG2_INIT = 0, |
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parameter REG3_INIT = 0, |
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parameter REG4_INIT = 0, |
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parameter REG5_INIT = 0, |
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parameter REG6_INIT = 0, |
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parameter REG7_INIT = 0, |
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parameter REG8_INIT = 0, |
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parameter REG9_INIT = 0, |
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parameter REGA_INIT = 0, |
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parameter REGB_INIT = 0, |
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parameter REGC_INIT = 0, |
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parameter REGD_INIT = 0, |
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parameter REGE_INIT = 0, |
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parameter REGF_INIT = 0 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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//regbus interface |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output [31:0] rd_data, //received serial data |
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output [31:0] reg0, |
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output [31:0] reg1, |
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output [31:0] reg2, |
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output [31:0] reg3, |
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output [31:0] reg4, |
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output [31:0] reg5, |
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output [31:0] reg6, |
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output [31:0] reg7, |
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output [31:0] reg8, |
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output [31:0] reg9, |
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output [31:0] regA, |
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output [31:0] regB, |
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output [31:0] regC, |
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output [31:0] regD, |
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output [31:0] regE, |
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output [31:0] regF |
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); |
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parameter REG_END_ADD = REG_START_ADD + 16 - 1; //寄存器结束地址 |
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reg [31:0] data[0:15] = 0; |
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assign reg0 = data[0]; |
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assign reg1 = data[1]; |
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assign reg2 = data[2]; |
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assign reg3 = data[3]; |
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assign reg4 = data[4]; |
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assign reg5 = data[5]; |
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assign reg6 = data[6]; |
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assign reg7 = data[7]; |
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assign reg8 = data[8]; |
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assign reg9 = data[9]; |
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assign regA = data[10]; |
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assign regB = data[11]; |
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assign regC = data[12]; |
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assign regD = data[13]; |
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assign regE = data[14]; |
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assign regF = data[15]; |
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integer i; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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data[0] <= REG0_INIT; |
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data[1] <= REG1_INIT; |
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data[2] <= REG2_INIT; |
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data[3] <= REG3_INIT; |
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data[4] <= REG4_INIT; |
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data[5] <= REG5_INIT; |
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data[6] <= REG6_INIT; |
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data[7] <= REG7_INIT; |
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data[8] <= REG8_INIT; |
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data[9] <= REG9_INIT; |
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data[10] <= REGA_INIT; |
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data[11] <= REGB_INIT; |
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data[12] <= REGC_INIT; |
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data[13] <= REGD_INIT; |
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data[14] <= REGE_INIT; |
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data[15] <= REGF_INIT; |
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end else begin |
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if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) |
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data[addr-REG_START_ADD] <= wr_data; |
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end |
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end |
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assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr-REG_START_ADD] : 31'b0; |
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endmodule |
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