diff --git a/led_test.pds b/led_test.pds index 3bebe77..65617b7 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 14:58:21 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 15:22:43 2024") (_version "1.0.5") (_status "initial") (_project @@ -27,7 +27,7 @@ ) (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-08T14:52:29") + (_timespec "2024-01-08T15:22:29") ) (_file "source/src/uart_tx.v" (_format verilog) @@ -47,7 +47,7 @@ ) (_file "source/src/spi_reg_reader.v" (_format verilog) - (_timespec "2024-01-07T20:01:06") + (_timespec "2024-01-08T15:19:56") ) (_file "source/src/src_ttl_parser.v" (_format verilog) @@ -91,7 +91,7 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-01-08T14:55:31") + (_timespec "2024-01-08T15:16:56") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) @@ -99,7 +99,7 @@ ) (_file "source/src/rd_data_router.v" (_format verilog) - (_timespec "2024-01-08T14:58:15") + (_timespec "2024-01-08T15:00:24") ) ) ) @@ -160,17 +160,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-08T14:58:18") + (_timespec "2024-01-08T15:22:40") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-08T14:58:18") + (_timespec "2024-01-08T15:22:39") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-08T14:58:19") + (_timespec "2024-01-08T15:22:40") ) ) ) @@ -180,13 +180,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 1)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) + (_db_output + (_file "synthesize/Top_syn.adf" + (_format adif) + (_timespec "2024-01-08T15:22:43") + ) + ) (_output + (_file "synthesize/Top_syn.vm" + (_format structural_verilog) + (_timespec "2024-01-08T15:22:43") + ) + (_file "synthesize/Top.snr" + (_format text) + (_timespec "2024-01-08T15:22:43") + ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-08T14:58:21") + (_timespec "2024-01-08T15:22:43") ) ) ) diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index a953761..176d6be 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -13,7 +13,7 @@ module ttl_output #( input rst_n, //asynchronous reset input, low active //寄存器读写接口 - output [31:0] addr, + input [31:0] addr, input [31:0] wr_data, input wr_en, output wire [31:0] rd_data, diff --git a/source/src/rd_data_router.v b/source/src/rd_data_router.v index 6711ee1..2151ba3 100644 --- a/source/src/rd_data_router.v +++ b/source/src/rd_data_router.v @@ -27,49 +27,27 @@ module rd_data_router ( output reg [31:0] rd_data_out ); - // //STM32寄存器地址 - // localparam REG_ADD_OFF_STM32 = 16'h0000; - // localparam REG_ADD_OFF_FPGA_TEST = 16'h00020; - // //控制中心寄存器地址 - // localparam REG_ADD_OFF_CONTROL_SENSOR = 16'h00030; - // //输入组件 - // localparam REG_ADD_OFF_TTLIN1 = 16'h0100; - // localparam REG_ADD_OFF_TTLIN2 = 16'h0110; - // localparam REG_ADD_OFF_TTLIN3 = 16'h0120; - // localparam REG_ADD_OFF_TTLIN4 = 16'h0130; - // localparam REG_ADD_OFF_TIMECODE_IN = 16'h0140; - // localparam REG_ADD_OFF_GENLOCK_IN = 16'h0150; - // //输出组件 - // localparam REG_ADD_OFF_TTLOUT1 = 16'h0200; - // localparam REG_ADD_OFF_TTLOUT2 = 16'h0210; - // localparam REG_ADD_OFF_TTLOUT3 = 16'h0220; - // localparam REG_ADD_OFF_TTLOUT4 = 16'h0230; - // localparam REG_ADD_OFF_TIMECODE_OUT = 16'h0240; - // localparam REG_ADD_OFF_GENLOCK_OUT = 16'h0250; - // localparam REG_ADD_OFF_STM32_IF = 16'h0260; - // //调试组件 - // localparam REG_ADD_OFF_DEBUGER = 16'h0300; always @(*) begin case (addr >> 8) - // `REG_ADD_OFF_STM32 >> 8: rd_data_out = stm32_rd_data; - // `REG_ADD_OFF_FPGA_TEST >> 8: rd_data_out = fpga_test_rd_data; - // `REG_ADD_OFF_CONTROL_SENSOR >> 8: rd_data_out = control_sensor_rd_data; - // `REG_ADD_OFF_TTLIN1 >> 8: rd_data_out = ttlin1_rd_data; - // `REG_ADD_OFF_TTLIN2 >> 8: rd_data_out = ttlin2_rd_data; - // `REG_ADD_OFF_TTLIN3 >> 8: rd_data_out = ttlin3_rd_data; - // `REG_ADD_OFF_TTLIN4 >> 8: rd_data_out = ttlin4_rd_data; - // `REG_ADD_OFF_TIMECODE_IN >> 8: rd_data_out = timecode_in_rd_data; - // `REG_ADD_OFF_GENLOCK_IN >> 8: rd_data_out = genlock_in_rd_data; - // `REG_ADD_OFF_TTLOUT1 >> 8: rd_data_out = ttlout1_rd_data; - // `REG_ADD_OFF_TTLOUT2 >> 8: rd_data_out = ttlout2_rd_data; - // `REG_ADD_OFF_TTLOUT3 >> 8: rd_data_out = ttlout3_rd_data; - // `REG_ADD_OFF_TTLOUT4 >> 8: rd_data_out = ttlout4_rd_data; - // `REG_ADD_OFF_TIMECODE_OUT >> 8: rd_data_out = timecode_out_rd_data; - // `REG_ADD_OFF_GENLOCK_OUT >> 8: rd_data_out = genlock_out_rd_data; - // `REG_ADD_OFF_STM32_IF >> 8: rd_data_out = stm32_if_rd_data; - // `REG_ADD_OFF_DEBUGER >> 8: rd_data_out = debuger_rd_data; + `REG_ADD_OFF_STM32 >> 8: rd_data_out = stm32_rd_data; + `REG_ADD_OFF_FPGA_TEST >> 8: rd_data_out = fpga_test_rd_data; + `REG_ADD_OFF_CONTROL_SENSOR >> 8: rd_data_out = control_sensor_rd_data; + `REG_ADD_OFF_TTLIN1 >> 8: rd_data_out = ttlin1_rd_data; + `REG_ADD_OFF_TTLIN2 >> 8: rd_data_out = ttlin2_rd_data; + `REG_ADD_OFF_TTLIN3 >> 8: rd_data_out = ttlin3_rd_data; + `REG_ADD_OFF_TTLIN4 >> 8: rd_data_out = ttlin4_rd_data; + `REG_ADD_OFF_TIMECODE_IN >> 8: rd_data_out = timecode_in_rd_data; + `REG_ADD_OFF_GENLOCK_IN >> 8: rd_data_out = genlock_in_rd_data; + `REG_ADD_OFF_TTLOUT1 >> 8: rd_data_out = ttlout1_rd_data; + `REG_ADD_OFF_TTLOUT2 >> 8: rd_data_out = ttlout2_rd_data; + `REG_ADD_OFF_TTLOUT3 >> 8: rd_data_out = ttlout3_rd_data; + `REG_ADD_OFF_TTLOUT4 >> 8: rd_data_out = ttlout4_rd_data; + `REG_ADD_OFF_TIMECODE_OUT >> 8: rd_data_out = timecode_out_rd_data; + `REG_ADD_OFF_GENLOCK_OUT >> 8: rd_data_out = genlock_out_rd_data; + `REG_ADD_OFF_STM32_IF >> 8: rd_data_out = stm32_if_rd_data; + `REG_ADD_OFF_DEBUGER >> 8: rd_data_out = debuger_rd_data; default: rd_data_out = 0; endcase end diff --git a/source/src/top.v b/source/src/top.v index 6bbe488..e5896aa 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -40,16 +40,16 @@ module Top ( * TTL_OUT * *******************************************************************************/ - input sync_ttl_out1, + output sync_ttl_out1, output sync_ttl_out1_state_led, - input sync_ttl_out2, + output sync_ttl_out2, output sync_ttl_out2_state_led, - input sync_ttl_out3, + output sync_ttl_out3, output sync_ttl_out3_state_led, - input sync_ttl_out4, + output sync_ttl_out4, output sync_ttl_out4_state_led, /******************************************************************************* @@ -179,29 +179,29 @@ module Top ( ); - rd_data_router rd_data_router_inst ( - .addr(reg_reader_bus_addr), - - .stm32_rd_data(stm32_if_rd_data), - .fpga_test_rd_data(fpga_test_rd_data), - .control_sensor_rd_data(control_sensor_rd_data), - .ttlin1_rd_data(ttlin1_rd_data), - .ttlin2_rd_data(ttlin2_rd_data), - .ttlin3_rd_data(ttlin3_rd_data), - .ttlin4_rd_data(ttlin4_rd_data), - .timecode_in_rd_data(timecode_in_rd_data), - .genlock_in_rd_data(genlock_in_rd_data), - .ttlout1_rd_data(ttlout1_rd_data), - .ttlout2_rd_data(ttlout2_rd_data), - .ttlout3_rd_data(ttlout3_rd_data), - .ttlout4_rd_data(ttlout4_rd_data), - .timecode_out_rd_data(timecode_out_rd_data), - .genlock_out_rd_data(genlock_out_rd_data), - .stm32_if_rd_data(stm32_if_rd_data), - .debuger_rd_data(debuger_rd_data), - - .rd_data_out(reg_reader_bus_rd_data) - ); + rd_data_router rd_data_router_inst ( + .addr(reg_reader_bus_addr), + + .stm32_rd_data(0), + .fpga_test_rd_data(fpga_test_rd_data), + .control_sensor_rd_data(control_sensor_rd_data), + .ttlin1_rd_data(ttlin1_rd_data), + .ttlin2_rd_data(ttlin2_rd_data), + .ttlin3_rd_data(ttlin3_rd_data), + .ttlin4_rd_data(ttlin4_rd_data), + .timecode_in_rd_data(timecode_in_rd_data), + .genlock_in_rd_data(genlock_in_rd_data), + .ttlout1_rd_data(ttlout1_rd_data), // ok + .ttlout2_rd_data(ttlout2_rd_data), // ok + .ttlout3_rd_data(ttlout3_rd_data), // ok + .ttlout4_rd_data(ttlout4_rd_data), // ok + .timecode_out_rd_data(timecode_out_rd_data), + .genlock_out_rd_data(genlock_out_rd_data), + .stm32_if_rd_data(stm32_if_rd_data), + .debuger_rd_data(debuger_rd_data), + + .rd_data_out(reg_reader_bus_rd_data) + ); /******************************************************************************* @@ -223,33 +223,82 @@ module Top ( * 输出组件 * *******************************************************************************/ - wire [7:0] ttl_output_trigger_signal_src; - genvar i; - - wire sync_ttl_out[0:3] = {sync_ttl_out1,sync_ttl_out2,sync_ttl_out3,sync_ttl_out4}; - wire sync_ttl_out_state_led[0:3] = {sync_ttl_out1_state_led,sync_ttl_out2_state_led,sync_ttl_out3_state_led,sync_ttl_out4_state_led}; - wire [31:0]ttloutx_rd_data [0:3] = {ttlout1_rd_data,ttlout2_rd_data,ttlout3_rd_data,ttlout4_rd_data}; - - generate - for (i = 0; i < 4; i = i + 1) begin - ttl_output #( - .REG_START_ADD(`REG_ADD_OFF_TTLIN1+i*16), - .TEST(HARDWARE_TEST_MODE) - ) ttl_output_1 ( - .clk (sys_clk), - .rst_n(rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttloutx_rd_data[i]), - - .signal_in(ttl_output_trigger_signal_src), - - .ttloutput(sync_ttl_out[i]), - .ttloutput_state_led(sync_ttl_out_state_led[i]) - ); - end - endgenerate + wire [7:0] ttl_output_signal_in; + + ttl_output #( + .REG_START_ADD(`REG_ADD_OFF_TTLIN1), + .TEST(HARDWARE_TEST_MODE) + ) ttl_output_1 ( + .clk (sys_clk), + .rst_n(rst_n), + + .addr(reg_reader_bus_addr), + .wr_data(reg_reader_bus_wr_data), + .wr_en(reg_reader_bus_wr_en), + .rd_data(ttlout1_rd_data), + + .signal_in(ttl_output_signal_in), + + .ttloutput(sync_ttl_out1), + .ttloutput_state_led(sync_ttl_out1_state_led) + ); + + ttl_output #( + .REG_START_ADD(`REG_ADD_OFF_TTLIN2), + .TEST(HARDWARE_TEST_MODE) + ) ttl_output_2 ( + .clk (sys_clk), + .rst_n(rst_n), + + .addr(reg_reader_bus_addr), + .wr_data(reg_reader_bus_wr_data), + .wr_en(reg_reader_bus_wr_en), + .rd_data(ttlout2_rd_data), + + .signal_in(ttl_output_signal_in), + + .ttloutput(sync_ttl_out2), + .ttloutput_state_led(sync_ttl_out2_state_led) + ); + + ttl_output #( + .REG_START_ADD(`REG_ADD_OFF_TTLIN3), + .TEST(HARDWARE_TEST_MODE) + ) ttl_output_3 ( + .clk (sys_clk), + .rst_n(rst_n), + + .addr(reg_reader_bus_addr), + .wr_data(reg_reader_bus_wr_data), + .wr_en(reg_reader_bus_wr_en), + .rd_data(ttlout3_rd_data), + + .signal_in(ttl_output_signal_in), + + .ttloutput(sync_ttl_out3), + .ttloutput_state_led(sync_ttl_out3_state_led) + ); + + ttl_output #( + .REG_START_ADD(`REG_ADD_OFF_TTLIN4), + .TEST(HARDWARE_TEST_MODE) + ) ttl_output_4 ( + .clk (sys_clk), + .rst_n(rst_n), + + .addr(reg_reader_bus_addr), + .wr_data(reg_reader_bus_wr_data), + .wr_en(reg_reader_bus_wr_en), + .rd_data(ttlout4_rd_data), + + .signal_in(ttl_output_signal_in), + + .ttloutput(sync_ttl_out4), + .ttloutput_state_led(sync_ttl_out4_state_led) + ); + + + + endmodule