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spi_reg_reader 仿真验证通过

master
zhaohe 2 years ago
parent
edc2742d06
commit
34fdb098df
6 changed files with 751 additions and 92 deletions
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  1. 106
      led_test.pds
  2. 288
      source/src/spi_reg_reader.v
  3. 259
      source/src/spi_reg_reader.v.bak
  4. 10
      source/src/top.v
  5. 90
      source/test/test_spi_reg_reader.v
  6. 90
      source/test/test_spi_reg_reader.v.bak

106
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Dec 15 09:34:17 2023")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Dec 15 22:11:17 2023")
(_version "1.0.5")
(_status "initial")
(_project
@ -27,7 +27,7 @@
)
(_file "source/src/top.v" + "Top"
(_format verilog)
(_timespec "2023-12-14T21:43:40")
(_timespec "2023-12-15T20:12:24")
)
(_file "source/src/uart_tx.v"
(_format verilog)
@ -45,6 +45,10 @@
(_format verilog)
(_timespec "2023-12-14T21:44:03")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
(_timespec "2023-12-15T22:06:08")
)
)
)
(_widget wgt_my_ips_src
@ -87,9 +91,13 @@
(_format verilog)
(_timespec "2023-12-13T21:56:53")
)
(_file "source/test/test_uart_reg_reader.v" + "test_uart_reg_reader:"
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
(_timespec "2023-12-15T22:09:19")
)
(_file "source/test/test_spi_reg_reader.v" + "test_spi_reg_reader:"
(_format verilog)
(_timespec "2023-12-15T09:33:30")
(_timespec "2023-12-15T22:10:16")
)
)
)
@ -100,17 +108,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2023-12-15T09:33:46")
(_timespec "2023-12-15T22:11:12")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2023-12-15T09:33:46")
(_timespec "2023-12-15T22:11:12")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2023-12-15T09:33:46")
(_timespec "2023-12-15T22:11:12")
)
)
)
@ -126,21 +134,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2023-12-15T09:33:49")
(_timespec "2023-12-15T22:11:14")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2023-12-15T09:33:49")
(_timespec "2023-12-15T22:11:14")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2023-12-15T09:33:50")
(_timespec "2023-12-15T22:11:14")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2023-12-15T09:33:50")
(_timespec "2023-12-15T22:11:14")
)
)
)
@ -157,34 +165,14 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2023-12-15T09:33:56")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2023-12-15T09:33:56")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2023-12-15T09:33:56")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2023-12-15T09:33:56")
)
)
(_gci_state (_integer 5))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2023-12-15T09:33:56")
(_timespec "2023-12-15T20:24:09")
)
)
)
@ -194,39 +182,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2023-12-15T09:34:12")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2023-12-15T09:34:12")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2023-12-15T09:34:12")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2023-12-15T09:34:12")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2023-12-15T09:34:05")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2023-12-15T09:34:12")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2023-12-15T09:34:13")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -235,24 +191,8 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 2))
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2023-12-15T09:34:16")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2023-12-15T09:34:16")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2023-12-15T09:34:17")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))

288
source/src/spi_reg_reader.v
View File

@ -0,0 +1,288 @@
module spi_reg_reader (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
//regbus interface
output reg [31:0] addr,
output reg [31:0] wr_data,
output reg wr_en,
input wire [31:0] rd_data, //received serial data
//
input wire spi_cs_pin,
input wire spi_clk_pin,
input wire spi_rx_pin,
output reg spi_tx_pin
);
parameter STATE_IDLE = 0;
parameter STATE_RECEIVE_ADD = 1;
parameter STATE_READ_REG = 2;
parameter STATE_TRANSMIT_DATA = 3;
parameter STATE_RECEIVE_DATA = 4;
parameter STATE_WRITE_REG = 5;
parameter ADDRESS_WIDTH_BYTE_NUM = 2;
//
// 捕获SPI_CS的下降沿 和 SPI_CLK的上升沿
// detect:
// spi_cs_negedge_tri
// spi_clk_posedge_tri
//
reg spi_cs_last_state = 0;
reg spi_clk_last_state = 0;
assign spi_clk_posedge_tri = spi_clk_pin & ~spi_clk_last_state;
assign spi_clk_negedge_tri = ~spi_clk_pin & spi_clk_last_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
spi_cs_last_state <= 1;
spi_clk_last_state <= 1;
end else begin
spi_cs_last_state <= spi_cs_pin;
spi_clk_last_state <= spi_clk_pin;
end
end
/*******************************************************************************
* SPI数据解析，及其部分状态更新 *
*******************************************************************************/
//
//
//
// cs : ----______________________________________________
// clk : ----------____----____----____----____----____----
// bitcnt : 0 1 2 ... 7 0
// rx : . . . . .
// tx : <======><======><======><======><======>
// valid : .
// byte_cnt: 0 1
//
reg [7:0] bit_cnt = 0;
reg first_edge = 1;
// first_edge 状态更新
// 1:在spi_cs下降沿时候更新为0
// 2:复位时候更新为1
// bit_cnt 状态更新
// 1:在spi_clk下降沿时候更新
// 2:first_edge == 1时候更新
//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
bit_cnt <= 0;
first_edge <= 1;
end else begin
if (spi_cs_pin) begin
bit_cnt <= 0;
first_edge <= 1;
end else begin
if (spi_clk_negedge_tri) begin
if (first_edge) begin
bit_cnt <= 0;
first_edge <= 0;
end else begin
if (bit_cnt == 7) bit_cnt <= 0;
else bit_cnt <= bit_cnt + 1;
end
end
end
end
end
//
// byte_cnt
// 1:在spi_clk下降沿时候更新
// 2:在bit_cnt == 7时候更新
//
reg [7:0] spi_byte_cnt = 0; //byte_cnt
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
spi_byte_cnt <= 0;
end else begin
if (spi_cs_pin) begin
spi_byte_cnt <= 0;
end else begin
if (spi_clk_negedge_tri && bit_cnt == 7) begin
spi_byte_cnt <= spi_byte_cnt + 1;
end
end
end
end
//
// spi_tx_1byte_data 发送
//
reg [7:0] spi_tx_1byte_data = 0;
always @(*) begin
spi_tx_pin <= spi_tx_1byte_data[bit_cnt];
end
//
// spi_rx_1byte_data
// spi_rx_1byte_data_valid
//
reg [7:0] spi_rx_1byte_data = 0;
reg spi_rx_1byte_data_valid = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
spi_rx_1byte_data <= 0;
spi_rx_1byte_data_valid <= 0;
end else begin
if (spi_cs_pin) begin
spi_rx_1byte_data <= 0;
spi_rx_1byte_data_valid <= 0;
end else begin
if (spi_clk_posedge_tri) begin
spi_rx_1byte_data[bit_cnt] <= spi_rx_pin;
end
if (spi_clk_negedge_tri && bit_cnt == 7) spi_rx_1byte_data_valid <= 1;
else spi_rx_1byte_data_valid <= 0;
end
end
end
/*******************************************************************************
* 缓存接收到的数据 *
*******************************************************************************/
reg [7:0] spi_rx_data_cache [0:4+4-1];
reg [7:0] rx_byte_count = 0;
genvar i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rx_byte_count <= 0;
spi_rx_data_cache[0] <= 0;
spi_rx_data_cache[1] <= 0;
spi_rx_data_cache[2] <= 0;
spi_rx_data_cache[3] <= 0;
spi_rx_data_cache[4] <= 0;
spi_rx_data_cache[5] <= 0;
spi_rx_data_cache[6] <= 0;
spi_rx_data_cache[7] <= 0;
end else begin
if (spi_cs_pin) begin
// 失能状态
rx_byte_count <= 0;
spi_rx_data_cache[0] <= 0;
spi_rx_data_cache[1] <= 0;
spi_rx_data_cache[2] <= 0;
spi_rx_data_cache[3] <= 0;
spi_rx_data_cache[4] <= 0;
spi_rx_data_cache[5] <= 0;
spi_rx_data_cache[6] <= 0;
spi_rx_data_cache[7] <= 0;
end else begin
// 选中状态
if (spi_rx_1byte_data_valid) begin
rx_byte_count <= rx_byte_count + 1;
if (rx_byte_count < ADDRESS_WIDTH_BYTE_NUM + 4) begin
spi_rx_data_cache[rx_byte_count] <= spi_rx_1byte_data;
end
end
end
end
end
/*******************************************************************************
* 自动设置SPI需要发送的数据 spi_tx_1byte_data *
*******************************************************************************/
always @(*) begin
case (spi_byte_cnt)
ADDRESS_WIDTH_BYTE_NUM + 0: spi_tx_1byte_data <= rd_data[7:0];
ADDRESS_WIDTH_BYTE_NUM + 1: spi_tx_1byte_data <= rd_data[15:8];
ADDRESS_WIDTH_BYTE_NUM + 2: spi_tx_1byte_data <= rd_data[23:16];
ADDRESS_WIDTH_BYTE_NUM + 3: spi_tx_1byte_data <= rd_data[31:24];
default: spi_tx_1byte_data <= 0;
endcase
end
/*******************************************************************************
* 自动设置addr数值 *
*******************************************************************************/
always @(*) begin
case (ADDRESS_WIDTH_BYTE_NUM)
0: begin
addr[7:0] <= 0;
addr[15:8] <= 0;
addr[23:16] <= 0;
addr[31:24] <= 0;
end
1: begin
addr[7:0] <= {1'b0, spi_rx_data_cache[0][6:0]};
addr[15:8] <= 0;
addr[23:16] <= 0;
addr[31:24] <= 0;
end
2: begin
addr[7:0] <= spi_rx_data_cache[0][7:0];
addr[15:8] <= {1'b0, spi_rx_data_cache[1][6:0]};
addr[23:16] <= 0;
addr[31:24] <= 0;
end
3: begin
addr[7:0] <= spi_rx_data_cache[0][7:0];
addr[15:8] <= spi_rx_data_cache[1][7:0];
addr[23:16] <= {1'b0, spi_rx_data_cache[2][6:0]};
addr[31:24] <= 0;
end
4: begin
addr[7:0] <= spi_rx_data_cache[0][7:0];
addr[15:8] <= spi_rx_data_cache[1][7:0];
addr[23:16] <= spi_rx_data_cache[2][7:0];
addr[31:24] <= {1'b0, spi_rx_data_cache[3][6:0]};
end
endcase
end
/*******************************************************************************
* wr_data *
*******************************************************************************/
always @(*) begin
wr_data[7:0] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM];
wr_data[15:8] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+1];
wr_data[23:16] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+2];
wr_data[31:24] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+3];
end
/*******************************************************************************
* wr_en *
*******************************************************************************/
reg has_trigger_wr_en = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
wr_en <= 0;
has_trigger_wr_en <= 0;
end else begin
if (spi_cs_pin) begin
wr_en <= 0;
has_trigger_wr_en <= 0;
end else if (!spi_cs_pin && //
!has_trigger_wr_en && //
spi_byte_cnt == ADDRESS_WIDTH_BYTE_NUM + 4 && //
spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM-1][7]) begin
wr_en <= 1;
has_trigger_wr_en <= 1;
end else begin
wr_en <= 0;
end
end
end
endmodule

259
source/src/spi_reg_reader.v.bak
View File

@ -0,0 +1,259 @@
module spi_reg_reader (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
//regbus interface
output reg [31:0] addr,
output reg [31:0] wr_data,
output reg wr_en,
input wire [31:0] rd_data, //received serial data
//
input wire spi_cs_pin,
input wire spi_clk_pin,
input wire spi_rx_pin,
output reg spi_tx_pin
);
parameter STATE_IDLE = 0;
parameter STATE_RECEIVE_ADD = 1;
parameter STATE_READ_REG = 2;
parameter STATE_TRANSMIT_DATA = 3;
parameter STATE_RECEIVE_DATA = 4;
parameter STATE_WRITE_REG = 5;
parameter ADDRESS_WIDTH_BYTE_NUM = 2;
//
// 捕获SPI_CS的下降沿 和 SPI_CLK的上升沿
// detect:
// spi_cs_negedge_tri
// spi_clk_posedge_tri
//
reg spi_cs_last_state = 0;
reg spi_clk_last_state = 0;
assign spi_clk_posedge_tri = spi_clk_pin & ~spi_clk_last_state;
assign spi_clk_negedge_tri = ~spi_clk_pin & spi_clk_last_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
spi_cs_last_state <= 1;
spi_clk_last_state <= 1;
end else begin
spi_cs_last_state <= spi_cs_pin;
spi_clk_last_state <= spi_clk_pin;
end
end
/*******************************************************************************
* SPI数据解析，及其部分状态更新 *
*******************************************************************************/
//
//
//
// cs : ----______________________________________________
// clk : ----------____----____----____----____----____----
// bitcnt : 0 1 2 ... 7 0
// rx : . . . . .
// tx : <======><======><======><======><======>
// valid : .
// byte_cnt: 0 1
//
reg [7:0] bit_cnt = 0;
reg first_edge = 1;
// first_edge 状态更新
// 1:在spi_cs下降沿时候更新为0
// 2:复位时候更新为1
// bit_cnt 状态更新
// 1:在spi_clk下降沿时候更新
// 2:first_edge == 1时候更新
//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
bit_cnt <= 0;
first_edge <= 1;
end else begin
if (spi_cs_pin) begin
bit_cnt <= 0;
first_edge <= 1;
end else begin
if (first_edge) begin
bit_cnt <= 0;
first_edge <= 0;
end else begin
if (spi_clk_negedge_tri) begin
if (bit_cnt == 7) bit_cnt <= 0;
else bit_cnt <= bit_cnt + 1;
end
end
end
end
end
//
// byte_cnt
// 1:在spi_clk下降沿时候更新
// 2:在bit_cnt == 7时候更新
//
reg [7:0] spi_byte_cnt = 0; //byte_cnt
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
spi_byte_cnt <= 0;
end else begin
if (spi_cs_pin) begin
spi_byte_cnt <= 0;
end else begin
if (spi_clk_negedge_tri && bit_cnt == 7) begin
spi_byte_cnt <= spi_byte_cnt + 1;
end
end
end
end
//
// spi_tx_1byte_data 发送
//
reg [7:0] spi_tx_1byte_data = 0;
always @(*) begin
spi_tx_pin <= spi_tx_1byte_data[bit_cnt];
end
//
// spi_rx_1byte_data
// spi_rx_1byte_data_valid
//
reg [7:0] spi_rx_1byte_data = 0;
reg spi_rx_1byte_data_valid = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
spi_rx_1byte_data <= 0;
spi_rx_1byte_data_valid <= 0;
end else begin
if (spi_cs_pin) begin
spi_rx_1byte_data <= 0;
spi_rx_1byte_data_valid <= 0;
end else begin
if (spi_clk_posedge_tri) begin
spi_rx_1byte_data[bit_cnt] <= spi_rx_pin;
end
if (spi_clk_negedge_tri && bit_cnt == 7) spi_rx_1byte_data_valid <= 1;
else spi_rx_1byte_data_valid <= 0;
end
end
end
/*******************************************************************************
* 缓存接收到的数据 *
*******************************************************************************/
reg [7:0] spi_rx_data_cache [0:ADDRESS_WIDTH_BYTE_NUM+4-1] = 0;
reg [7:0] rx_byte_count = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rx_byte_count <= 0;
spi_rx_data_cache[0] <= 0;
spi_rx_data_cache[1] <= 0;
spi_rx_data_cache[2] <= 0;
spi_rx_data_cache[3] <= 0;
spi_rx_data_cache[4] <= 0;
spi_rx_data_cache[5] <= 0;
end else begin
if (spi_cs_pin) begin
// 失能状态
rx_byte_count <= 0;
spi_rx_data_cache[0] <= 0;
spi_rx_data_cache[1] <= 0;
spi_rx_data_cache[2] <= 0;
spi_rx_data_cache[3] <= 0;
spi_rx_data_cache[4] <= 0;
spi_rx_data_cache[5] <= 0;
end else begin
// 选中状态
if (spi_rx_1byte_data_valid) begin
rx_byte_count <= rx_byte_count + 1;
if (rx_byte_count < ADDRESS_WIDTH_BYTE_NUM + 4) begin
spi_rx_data_cache[rx_byte_count] <= spi_rx_1byte_data;
end
end
end
end
end
/*******************************************************************************
* 自动设置SPI需要发送的数据 spi_tx_1byte_data *
*******************************************************************************/
always @(*) begin
case (spi_byte_cnt)
ADDRESS_WIDTH_BYTE_NUM + 0: spi_tx_1byte_data <= rd_data[7:0];
ADDRESS_WIDTH_BYTE_NUM + 1: spi_tx_1byte_data <= rd_data[15:8];
ADDRESS_WIDTH_BYTE_NUM + 2: spi_tx_1byte_data <= rd_data[23:16];
ADDRESS_WIDTH_BYTE_NUM + 3: spi_tx_1byte_data <= rd_data[31:24];
default: spi_tx_1byte_data <= 0;
endcase
end
/*******************************************************************************
* 自动设置addr数值 *
*******************************************************************************/
always @(*) begin
case (ADDRESS_WIDTH_BYTE_NUM)
0: begin
addr[6:0] <= spi_rx_data_cache[0][6:0];
end
1: begin
addr[7:0] <= spi_rx_data_cache[0][7:0];
addr[14:8] <= spi_rx_data_cache[1][6:0];
end
2: begin
addr[7:0] <= spi_rx_data_cache[0][7:0];
addr[15:8] <= spi_rx_data_cache[1][7:0];
addr[22:16] <= spi_rx_data_cache[2][6:0];
end
3: begin
addr[7:0] <= spi_rx_data_cache[0][7:0];
addr[15:8] <= spi_rx_data_cache[1][7:0];
addr[23:16] <= spi_rx_data_cache[2][7:0];
addr[30:24] <= spi_rx_data_cache[3][6:0];
end
endcase
end
/*******************************************************************************
* wr_data *
*******************************************************************************/
always @(*) begin
wr_data[7:0] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM];
wr_data[15:8] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+1];
wr_data[23:16] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+2];
wr_data[31:24] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+3];
end
/*******************************************************************************
* wr_en *
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
wr_en <= 0;
end else begin
if (!spi_cs_pin && spi_clk_negedge_tri && spi_byte_cnt == ADDRESS_WIDTH_BYTE_NUM + 4) begin
wr_en <= 1;
end else begin
wr_en <= 0;
end
end
end
endmodule

10
source/src/top.v
View File

@ -14,15 +14,7 @@ module Top (
.clkout0(inclkpll_clk0out)
);
uart_reg_reader uart_reg_reader_impl (
.clk(sys_clk),
.rst_n(rst_n),
.reg_data(),
.reg_add(),
.reg_add_valid(),
.uart_rx_pin(usb_serial_rx),
.uart_tx_pin(usb_serial_tx)
);
monitor_line monitor_line_usb_serial_rx(sys_clk, rst_n, usb_serial_rx, test_io[4]);
assign test_io[3] = usb_serial_tx;

90
source/test/test_spi_reg_reader.v
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@ -0,0 +1,90 @@
`timescale 1ns / 1ns
module test_spi_reg_reader;
// input clk,
// input rst_n,
// output reg [31:0] addr,
// output reg [31:0] wr_data,
// output reg wr_en,
// input wire [31:0] rd_data,
// input wire spi_cs_pin,
// input wire spi_clk_pin,
// input wire spi_rx_pin,
// output reg spi_tx_pin
reg clk_50m;
reg rst_n;
wire [31:0] addr;
wire [31:0] wr_data;
wire wr_en;
reg [31:0] rd_data;
reg spi_cs_pin;
reg spi_clk_pin;
reg spi_rx_pin;
wire spi_tx_pin;
spi_reg_reader spi_reg_reader_impl (
.clk(clk_50m),
.rst_n(rst_n),
.addr(addr),
.wr_data(wr_data),
.wr_en(wr_en),
.rd_data(rd_data),
.spi_cs_pin(spi_cs_pin),
.spi_clk_pin(spi_clk_pin),
.spi_rx_pin(spi_rx_pin),
.spi_tx_pin(spi_tx_pin)
);
// reg rst_n;
// reg [31:0] rd_data;
// reg spi_tx_pin;
// reg clk_50m;
// reg spi_cs_pin;
// reg spi_clk_pin;
// reg spi_rx_pin;
always #10 clk_50m = ~clk_50m; //20ns 50MHZ
integer i = 0;
reg [63:0] txdata = 64'h88_77_66_55_44_33_82_11;
initial begin
rst_n <= 0;
clk_50m <= 0;
spi_cs_pin <= 1;
spi_clk_pin <= 1;
spi_rx_pin <= 0;
rd_data <= 32'h11223344;
#100;
rst_n <= 1;
#100;
spi_cs_pin <= 0;
#100;
repeat (64) begin
spi_clk_pin <= 0;
spi_rx_pin <= txdata[i];
#200;
spi_clk_pin <= 1;
i = i + 1;
#200;
end
spi_clk_pin <= 0;
#200;
spi_clk_pin <= 1;
#200;
spi_cs_pin <= 1;
#1000;
$stop;
end
endmodule

90
source/test/test_spi_reg_reader.v.bak
View File

@ -0,0 +1,90 @@
`timescale 1ns / 1ns
module test_spi_reg_reader;
// input clk,
// input rst_n,
// output reg [31:0] addr,
// output reg [31:0] wr_data,
// output reg wr_en,
// input wire [31:0] rd_data,
// input wire spi_cs_pin,
// input wire spi_clk_pin,
// input wire spi_rx_pin,
// output reg spi_tx_pin
reg clk_50m;
reg rst_n;
wire [31:0] addr;
wire [31:0] wr_data;
wire wr_en;
reg [31:0] rd_data;
reg spi_cs_pin;
reg spi_clk_pin;
reg spi_rx_pin;
wire spi_tx_pin;
spi_reg_reader spi_reg_reader_impl (
.clk(clk_50m),
.rst_n(rst_n),
.addr(addr),
.wr_data(wr_data),
.wr_en(wr_en),
.rd_data(rd_data),
.spi_cs_pin(spi_cs_pin),
.spi_clk_pin(spi_clk_pin),
.spi_rx_pin(spi_rx_pin),
.spi_tx_pin(spi_tx_pin)
);
// reg rst_n;
// reg [31:0] rd_data;
// reg spi_tx_pin;
// reg clk_50m;
// reg spi_cs_pin;
// reg spi_clk_pin;
// reg spi_rx_pin;
always #10 clk_50m = ~clk_50m; //20ns 50MHZ
integer i = 0;
reg [63:0] txdata = 64'h11_22_33_44_55_66_77_88
initial begin
rst_n <= 0;
clk_50m <= 0;
spi_cs_pin <= 1;
spi_clk_pin <= 1;
spi_rx_pin <= 0;
rd_data <= 32'h11223344;
#100;
rst_n <= 1;
#100;
spi_cs_pin <= 0;
#100;
repeat (64) begin
spi_clk_pin <= 0;
spi_rx_pin <= txdata[i];
#200;
spi_clk_pin <= 1;
i = i + 1;
#200;
end
spi_clk_pin <= 0;
#200;
spi_clk_pin <= 1;
#200;
spi_cs_pin <= 1;
#1000;
$stop;
end
endmodule
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