diff --git a/led_test.fdc b/led_test.fdc index c292cfa..6dd4b39 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -1,7 +1,85 @@ -define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:rst_n} {PAP_IO_LOC} {U12} -define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} -define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} +# debug_signal_output[0] output M18 +# debug_signal_output[1] output K18 +# debug_signal_output[2] output K17 +# debug_signal_output[3] output H18 +# debug_signal_output[4] output H17 +# debug_signal_output[5] output G18 +# debug_signal_output[6] output G17 +# debug_signal_output[7] output F18 +# debug_signal_output[8] output F17 +# debug_signal_output[9] output G16 +# debug_signal_output[10] output F16 +# debug_signal_output[11] output H16 +# debug_signal_output[12] output J16 +# debug_signal_output[13] output C17 +# debug_signal_output[14] output C18 +# debug_signal_output[15] output A18 +# genlock_out_dac[0] OUTPUT A16 +# genlock_out_dac[1] OUTPUT B16 +# genlock_out_dac[2] OUTPUT A15 +# genlock_out_dac[3] OUTPUT B15 +# genlock_out_dac[4] OUTPUT A14 +# genlock_out_dac[5] OUTPUT B14 +# genlock_out_dac[6] OUTPUT A12 +# genlock_out_dac[7] OUTPUT B12 +# genlock_out_dac[8] OUTPUT A11 +# genlock_out_dac[9] OUTPUT B11 +# genlock_out_dac_clk OUTPUT H13 +# genlock_out_dac_state_led OUTPUT D17 +# stm32if_camera_sync_out OUTPUT C10 +# stm32if_start_signal_out OUTPUT F12 +# stm32if_timecode_sync_out OUTPUT G12 +# stm32if_timecode_add[0] OUTPUT D13 +# stm32if_timecode_add[1] OUTPUT D15 +# stm32if_timecode_add[2] OUTPUT C15 +# stm32if_timecode_add[3] OUTPUT E15 +# stm32if_timecode_data[0] OUTPUT E16 +# stm32if_timecode_data[1] OUTPUT A17 +# stm32if_timecode_data[2] OUTPUT B17 +# stm32if_timecode_data[3] OUTPUT B18 +# spi2_cs_pin INPUT V14 +# spi2_clk_pin INPUT V13 +# spi2_rx_pin INPUT U14 +# spi2_tx_pin OUTPUT U13 +# spi1_cs_pin INPUT P17 +# spi1_clk_pin INPUT L12 +# spi1_rx_pin INPUT R18 +# spi1_tx_pin OUTPUT R17 +# sync_ttl_in1 INPUT R11 +# sync_ttl_in1_state_led OUTPUT U10 +# sync_ttl_in2 INPUT P11 +# sync_ttl_in2_state_led OUTPUT V10 +# sync_ttl_in3 INPUT R13 +# sync_ttl_in3_state_led OUTPUT U11 +# sync_ttl_in4 INPUT R14 +# sync_ttl_in4_state_led OUTPUT U12 +# sync_ttl_out1 OUTPUT V17 +# sync_ttl_out1_state_led OUTPUT L18 +# sync_ttl_out2 OUTPUT T17 +# sync_ttl_out2_state_led OUTPUT L17 +# sync_ttl_out3 OUTPUT U17 +# sync_ttl_out3_state_led OUTPUT N16 +# sync_ttl_out4 OUTPUT M13 +# sync_ttl_out4_state_led OUTPUT N15 +# genlock_in_hsync INPUT U16 +# genlock_in_vsync INPUT V16 +# genlock_in_fsync INPUT T16 +# genlock_in_state_led OUTPUT N14 +# timecode_out_bnc OUTPUT L15 +# timecode_out_bnc_select OUTPUT A10 +# timecode_out_bnc_state_led OUTPUT E17 +# timecode_out_headphone OUTPUT N18 +# timecode_out_headphone_select OUTPUT B10 +# timecode_out_headphone_state_led OUTPUT E18 +# timecode_headphone_in INPUT R16 +# timecode_headphone_in_state_led OUTPUT V12 +# timecode_bnc_in INPUT R15 +# timecode_bnc_in_state_led INPUT D18 + +# define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:rst_n} {PAP_IO_LOC} {G13} +# define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:sys_clk} {PAP_IO_LOC} {B5} define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3} @@ -12,21 +90,466 @@ define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} -define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {U13} -define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} -define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} -define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V13} -define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {U13} +# define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} +# define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V13} +# define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {V14} +# define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {U14} +# define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {M18} +define_attribute {p:debug_signal_output[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[0]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[0]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[0]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[1]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[1]} {PAP_IO_LOC} {K18} +define_attribute {p:debug_signal_output[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[1]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[1]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[1]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[2]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[2]} {PAP_IO_LOC} {K17} +define_attribute {p:debug_signal_output[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[2]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[2]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[2]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[3]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[3]} {PAP_IO_LOC} {H18} +define_attribute {p:debug_signal_output[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[3]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[3]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[3]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[4]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[4]} {PAP_IO_LOC} {H17} +define_attribute {p:debug_signal_output[4]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[4]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[4]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[4]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[5]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[5]} {PAP_IO_LOC} {G18} +define_attribute {p:debug_signal_output[5]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[5]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[5]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[5]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[6]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[6]} {PAP_IO_LOC} {G17} +define_attribute {p:debug_signal_output[6]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[6]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[6]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[6]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[7]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[7]} {PAP_IO_LOC} {F18} +define_attribute {p:debug_signal_output[7]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[7]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[7]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[7]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[8]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[8]} {PAP_IO_LOC} {F17} +define_attribute {p:debug_signal_output[8]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[8]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[8]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[8]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[9]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[9]} {PAP_IO_LOC} {G16} +define_attribute {p:debug_signal_output[9]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[9]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[9]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[9]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[10]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[10]} {PAP_IO_LOC} {F16} +define_attribute {p:debug_signal_output[10]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[10]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[10]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[10]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[11]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[11]} {PAP_IO_LOC} {H16} +define_attribute {p:debug_signal_output[11]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[11]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[11]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[11]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[12]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[12]} {PAP_IO_LOC} {J16} +define_attribute {p:debug_signal_output[12]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[12]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[12]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[12]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[13]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[13]} {PAP_IO_LOC} {C17} +define_attribute {p:debug_signal_output[13]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[13]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[13]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[13]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[14]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[14]} {PAP_IO_LOC} {C18} +define_attribute {p:debug_signal_output[14]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[14]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[14]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[14]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[15]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[15]} {PAP_IO_LOC} {A18} +define_attribute {p:debug_signal_output[15]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[15]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[15]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[15]} {PAP_IO_SLEW} {SLOW} + + + +define_attribute {p:genlock_out_dac[0]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_LOC} {A16} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_LOC} {B16} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_LOC} {A15} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_LOC} {B15} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_LOC} {A14} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_LOC} {B14} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_LOC} {A12} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_LOC} {B12} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_LOC} {A11} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac[9]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac[9]} {PAP_IO_LOC} {B11} +define_attribute {p:genlock_out_dac[9]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[9]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac[9]} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac[9]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_LOC} {H13} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_out_dac_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_out_dac_state_led} {PAP_IO_LOC} {D17} +define_attribute {p:genlock_out_dac_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_out_dac_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_out_dac_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {C10} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {F12} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {G12} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_LOC} {D13} +define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_LOC} {D15} +define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_LOC} {C15} +define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_LOC} {E15} +define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_LOC} {E16} +define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_LOC} {A17} +define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_LOC} {B17} +define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_LOC} {B18} +define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_SLEW} {SLOW} define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {V14} +define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {P17} define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {L12} +define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {U14} +define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {R18} define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {R17} +define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} +define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} +define_attribute {p:spi2_cs_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi2_cs_pin} {PAP_IO_LOC} {V14} +define_attribute {p:spi2_cs_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi2_cs_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi2_clk_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi2_clk_pin} {PAP_IO_LOC} {V13} +define_attribute {p:spi2_clk_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi2_clk_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi2_rx_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi2_rx_pin} {PAP_IO_LOC} {U14} +define_attribute {p:spi2_rx_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi2_rx_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi2_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:spi2_tx_pin} {PAP_IO_LOC} {U13} +define_attribute {p:spi2_tx_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi2_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:spi2_tx_pin} {PAP_IO_DRIVE} {4} +define_attribute {p:spi2_tx_pin} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_in1} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:sync_ttl_in1} {PAP_IO_LOC} {R11} +define_attribute {p:sync_ttl_in1} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in1} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_LOC} {U10} +define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_in2} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:sync_ttl_in2} {PAP_IO_LOC} {P11} +define_attribute {p:sync_ttl_in2} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in2} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_LOC} {V10} +define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_in3} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {R13} +define_attribute {p:sync_ttl_in3} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in3} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_LOC} {U11} +define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_in4} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {R14} +define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_LOC} {U12} +define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {V17} +define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out1} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_LOC} {L18} +define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_out2} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {T17} +define_attribute {p:sync_ttl_out2} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out2} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out2} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_LOC} {L17} +define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_out3} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {U17} +define_attribute {p:sync_ttl_out3} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW} + + +define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_LOC} {N16} +define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {M13} +define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out4} {PAP_IO_SLEW} {SLOW} +define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_LOC} {N15} +define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:genlock_in_hsync} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {U16} +define_attribute {p:genlock_in_hsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_hsync} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:genlock_in_vsync} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {V16} +define_attribute {p:genlock_in_vsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_vsync} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:genlock_in_fsync} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {T16} +define_attribute {p:genlock_in_fsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_fsync} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:genlock_in_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:genlock_in_state_led} {PAP_IO_LOC} {N14} +define_attribute {p:genlock_in_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:genlock_in_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:genlock_in_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:timecode_out_bnc} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {L15} +define_attribute {p:timecode_out_bnc} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_out_bnc} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_bnc} {PAP_IO_SLEW} {SLOW} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {A10} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_SLEW} {SLOW} +define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_LOC} {E17} +define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:timecode_out_headphone} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {N18} +define_attribute {p:timecode_out_headphone} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_out_headphone} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_headphone} {PAP_IO_SLEW} {SLOW} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {B10} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_SLEW} {SLOW} +define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_LOC} {E18} +define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_SLEW} {SLOW} + + +define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {R16} +define_attribute {p:timecode_headphone_in} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_headphone_in} {PAP_IO_STANDARD} {LVTTL33} + +define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_LOC} {V12} +define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_SLEW} {SLOW} + +define_attribute {p:timecode_bnc_in} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {R15} +define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_LOC} {D18} +define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:rst_n} {PAP_IO_LOC} {G13} +define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} +define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} diff --git a/led_test.pds b/led_test.pds index 65617b7..d71ee44 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 15:22:43 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 16:51:44 2024") (_version "1.0.5") (_status "initial") (_project @@ -27,7 +27,7 @@ ) (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-08T15:22:29") + (_timespec "2024-01-08T16:08:57") ) (_file "source/src/uart_tx.v" (_format verilog) @@ -117,7 +117,7 @@ (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2024-01-07T14:16:20") + (_timespec "2024-01-08T16:41:31") ) ) ) @@ -160,17 +160,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-08T15:22:40") + (_timespec "2024-01-08T16:51:24") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-08T15:22:39") + (_timespec "2024-01-08T16:51:23") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-08T15:22:40") + (_timespec "2024-01-08T16:51:24") ) ) ) @@ -186,21 +186,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-01-08T15:22:43") + (_timespec "2024-01-08T16:51:27") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-01-08T15:22:43") + (_timespec "2024-01-08T16:51:27") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-01-08T15:22:43") + (_timespec "2024-01-08T16:51:27") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-08T15:22:43") + (_timespec "2024-01-08T16:51:27") ) ) ) @@ -217,14 +217,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2024-01-08T16:51:29") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2024-01-08T16:51:29") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2024-01-08T16:51:29") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2024-01-08T16:51:29") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-07T20:01:36") + (_timespec "2024-01-08T16:51:29") ) ) ) @@ -234,7 +254,39 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-01-08T16:51:35") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-01-08T16:51:35") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-01-08T16:51:35") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-01-08T16:51:35") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-01-08T16:51:34") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-01-08T16:51:35") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-01-08T16:51:35") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -243,8 +295,24 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_attribute _auto_exe_lock (_switch OFF)) + (_db_output + (_file "report_timing/Top_rtp.adf" + (_format adif) + (_timespec "2024-01-08T16:51:38") + ) + ) + (_output + (_file "report_timing/Top.rtr" + (_format text) + (_timespec "2024-01-08T16:51:38") + ) + (_file "report_timing/rtr.db" + (_format text) + (_timespec "2024-01-08T16:51:38") + ) + ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -262,7 +330,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-01-08T16:51:43") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-01-08T16:51:43") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-01-08T16:51:43") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-01-08T16:51:44") + ) + ) ) ) ) diff --git a/pin.md b/pin.md new file mode 100644 index 0000000..47f5564 --- /dev/null +++ b/pin.md @@ -0,0 +1,6 @@ +``` + + + + +``` \ No newline at end of file diff --git a/source/src/top.v b/source/src/top.v index e5896aa..dfacfa7 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -10,30 +10,31 @@ module Top ( input genlock_in_hsync, input genlock_in_vsync, input genlock_in_fsync, - output genlock_state_led, + output genlock_in_state_led, /******************************************************************************* * GENLOCK_OUTPUT * *******************************************************************************/ - output [12:0] genlock_out_dac, - output genlock_out_dac_state_led, + output [9:0] genlock_out_dac, + output genlock_out_dac_clk, + output genlock_out_dac_state_led, /******************************************************************************* * TTL_IN * *******************************************************************************/ input sync_ttl_in1, - output sync_ttl_state_led1, + output sync_ttl_in1_state_led, input sync_ttl_in2, - output sync_ttl_state_led2, + output sync_ttl_in2_state_led, input sync_ttl_in3, - output sync_ttl_state_led3, + output sync_ttl_in3_state_led, input sync_ttl_in4, - output sync_ttl_state_led4, + output sync_ttl_in4_state_led, /******************************************************************************* @@ -56,21 +57,21 @@ module Top ( * TIMECODE_IN * *******************************************************************************/ input timecode_headphone_in, - input timecode_headphone_in_state_led, + output timecode_headphone_in_state_led, input timecode_bnc_in, - input timecode_bnc_in_state_led, + output timecode_bnc_in_state_led, /******************************************************************************* * TIMECODE_OUTPUT * *******************************************************************************/ - output timecode_bnc_out, - output timecode_bnc_output_select, - output timecode_bnc_out_state_led, + output timecode_out_bnc, + output timecode_out_bnc_select, + output timecode_out_bnc_state_led, - output timecode_headphone_out, - output timecode_headphone_output_select, - output timecode_headphone_out_state_led, + output timecode_out_headphone, + output timecode_out_headphone_select, + output timecode_out_headphone_state_led, /******************************************************************************* * STM32_IF * @@ -298,7 +299,4 @@ module Top ( ); - - - endmodule