9 changed files with 432 additions and 232 deletions
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59README.md
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120led_test.pds
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16source/src/output/ttl_output.v
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245source/src/top.v
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17source/src/zutils/zutils_multiplexer_2t1.v
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114source/src/zutils/zutils_multiplexer_32t1.v
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1source/src/zutils/zutils_multiplexer_4t1.v
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36source/src/zutils/zutils_muti_debug_signal_gen.v
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54source/src/zutils/zutils_pluse_generator.v
@ -0,0 +1,17 @@ |
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module zutils_multiplexer_2t1 ( |
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input choose, |
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input wire signal0, |
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input wire signal1, |
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output reg signalout |
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); |
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always @(*) begin |
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case (choose) |
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0: begin |
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signalout = signal0; |
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end |
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1: begin |
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signalout = signal1; |
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end |
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endcase |
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end |
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endmodule |
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@ -0,0 +1,114 @@ |
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module zutils_multiplexer_32t1 ( |
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input [31:0] chooseindex, |
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input wire [31:0] signal, |
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output reg signalout |
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); |
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always @(*) begin |
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case (chooseindex) |
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0: begin |
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signalout = signal[0]; |
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end |
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1: begin |
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signalout = signal[1]; |
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end |
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2: begin |
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signalout = signal[2]; |
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end |
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3: begin |
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signalout = signal[3]; |
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end |
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4: begin |
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signalout = signal[4]; |
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end |
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5: begin |
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signalout = signal[5]; |
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end |
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6: begin |
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signalout = signal[6]; |
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end |
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7: begin |
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signalout = signal[7]; |
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end |
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8: begin |
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signalout = signal[8]; |
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end |
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9: begin |
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signalout = signal[9]; |
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end |
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10: begin |
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signalout = signal[10]; |
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end |
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11: begin |
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signalout = signal[11]; |
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end |
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12: begin |
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signalout = signal[12]; |
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end |
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13: begin |
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signalout = signal[13]; |
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end |
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14: begin |
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signalout = signal[14]; |
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end |
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15: begin |
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signalout = signal[15]; |
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end |
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|
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16: begin |
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signalout = signal[16]; |
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end |
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17: begin |
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signalout = signal[17]; |
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end |
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18: begin |
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signalout = signal[18]; |
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end |
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19: begin |
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signalout = signal[19]; |
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end |
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20: begin |
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signalout = signal[20]; |
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end |
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21: begin |
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signalout = signal[21]; |
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end |
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22: begin |
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signalout = signal[22]; |
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end |
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23: begin |
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signalout = signal[23]; |
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end |
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24: begin |
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signalout = signal[24]; |
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end |
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25: begin |
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signalout = signal[25]; |
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end |
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26: begin |
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signalout = signal[26]; |
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end |
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27: begin |
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signalout = signal[27]; |
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end |
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28: begin |
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signalout = signal[28]; |
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end |
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29: begin |
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signalout = signal[29]; |
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end |
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30: begin |
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signalout = signal[30]; |
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end |
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31: begin |
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signalout = signal[31]; |
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end |
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default: begin |
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signalout = 0; |
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end |
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endcase |
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end |
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endmodule |
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@ -0,0 +1,36 @@ |
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module zutils_muti_debug_signal_gen #( |
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parameter SYS_CLOCK_FREQ = 50000000 |
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) ( |
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input clk, |
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input rst_n, |
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|
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input testflag, |
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input [31:0] rawsig, |
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output wire [31:0] output_signal |
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); |
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wire [31:0] output_debug_signal; |
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genvar gv_i; |
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generate |
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for (gv_i = 0; gv_i < 32; gv_i = gv_i + 1) begin |
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zutils_pwm_generator #( |
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
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.OUTPUT_FREQ((gv_i + 1) * 100) |
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) pwm_gen ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.output_signal(output_debug_signal[gv_i]) |
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); |
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zutils_multiplexer_2t1 mux ( |
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.choose(testflag), |
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.signal0(rawsig[gv_i]), |
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.signal1(output_debug_signal[gv_i]), |
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.signalout(output_signal[gv_i]) |
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); |
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end |
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endgenerate |
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endmodule |
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