5 changed files with 411 additions and 84 deletions
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96led_test.fdc
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126led_test.pds
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164source/src/timecode_output.v
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99source/src/top.v
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10source/src/zutils/zutils_pluse_generator.v
@ -0,0 +1,164 @@ |
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module timecode_output #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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//寄存器读写接口 |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output wire [31:0] rd_data, |
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|
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/******************************************************************************* |
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* TIMECODE输出 * |
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*******************************************************************************/ |
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input [31:0] ext_timecode_format, |
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input [63:0] ext_timecode_data, |
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input ext_timecode_tigger_sig, |
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input ext_timecode_serial_data, |
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|
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input [63:0] internal_timecode_data, |
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input internal_timecode_tigger_sig, |
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input [31:0] internal_timecode_format, |
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input internal_timecode_serial_data, |
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|
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/******************************************************************************* |
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* 输出接口 * |
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*******************************************************************************/ |
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output stm32if_timecode_tigger_sig, |
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|
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output reg timecode_out_bnc, |
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output reg timecode_out_bnc_select, // 电平选择 0line,1:mic |
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output reg timecode_out_bnc_state_led, |
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|
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output reg timecode_out_headphone, |
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output reg timecode_out_headphone_select, // 电平选择 0line,1:mic |
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output reg timecode_out_headphone_state_led |
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|
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); |
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// 1ms |
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reg [31:0] r0_timecode_select; //时码输入选择器 |
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reg [31:0] r1_timecode0; //时码原始码0 //注意这个数据要比ext_timecode_serial_data晚一帧 |
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reg [31:0] r2_timecode1; //时码原始码1 //注意这个数据要比ext_timecode_serial_data晚一帧 |
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reg [31:0] r3_timecode_format; // |
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reg [31:0] r4_bnc_outut_level_select; // 0:line, 1:mic |
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reg [31:0] r5_headphone_outut_level_select; // 0:line, 1:mic |
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|
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wire [31:0] reg_wr_index; |
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|
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.addr(addr), |
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.wr_data(wr_data), |
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.wr_en(wr_en), |
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.rd_data(rd_data), |
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|
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.reg0(r0_timecode_select), |
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.reg1(r1_timecode0), |
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.reg2(r2_timecode1), |
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.reg3(r3_timecode_format), |
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.reg4(r4_bnc_outut_level_select), |
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.reg5(r5_headphone_outut_level_select), |
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|
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|
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r0_timecode_select <= 0; |
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r4_bnc_outut_level_select <= 0; |
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r5_headphone_outut_level_select <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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31'h0: r0_timecode_select <= wr_data; |
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31'h4: r4_bnc_outut_level_select <= wr_data; |
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31'h5: r5_headphone_outut_level_select <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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|
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|
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reg out_timecode_serial_data; |
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reg timecode_tigger_sig; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r1_timecode0 <= 0; |
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r2_timecode1 <= 0; |
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r3_timecode_format <= 0; |
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out_timecode_serial_data <= 0; |
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timecode_tigger_sig <= 0; |
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end else begin |
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case (r0_timecode_select) |
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0: begin |
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r1_timecode0 <= 0; |
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r2_timecode1 <= 0; |
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r3_timecode_format <= 0; |
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out_timecode_serial_data <= 0; |
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timecode_tigger_sig <= 0; |
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end |
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// 内部时码 |
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1: begin |
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r1_timecode0 <= internal_timecode_data[31:0]; |
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r2_timecode1 <= internal_timecode_data[63:32]; |
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r3_timecode_format <= internal_timecode_format; |
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out_timecode_serial_data <= internal_timecode_serial_data; |
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timecode_tigger_sig <= internal_timecode_tigger_sig; |
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end |
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// 外部时码 |
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2: begin |
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r1_timecode0 <= ext_timecode_data[31:0]; |
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r2_timecode1 <= ext_timecode_data[63:32]; |
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r3_timecode_format <= ext_timecode_format; |
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out_timecode_serial_data <= ext_timecode_serial_data; |
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timecode_tigger_sig <= ext_timecode_tigger_sig; |
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end |
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|
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default: begin |
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r1_timecode0 <= 0; |
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r2_timecode1 <= 0; |
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r3_timecode_format <= 0; |
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out_timecode_serial_data <= 0; |
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timecode_tigger_sig <= 0; |
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end |
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endcase |
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end |
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end |
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|
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|
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zutils_pluse_generator _pluse_generator ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.pluse_width(1000), //1ms |
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.pluse_delay(32'd0), |
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.trigger(timecode_tigger_sig), |
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.output_signal(stm32if_timecode_tigger_sig) |
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); |
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always @(*) begin |
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timecode_out_bnc <= out_timecode_serial_data; |
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timecode_out_bnc_select <= r4_bnc_outut_level_select[0]; |
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timecode_out_bnc_state_led <= 1; |
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timecode_out_headphone <= out_timecode_serial_data; |
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timecode_out_headphone_select <= r5_headphone_outut_level_select[0]; |
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timecode_out_headphone_state_led <= 1; |
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end |
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endmodule |
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