diff --git a/led_test.pds b/led_test.pds
index 5786cad..b5348b1 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Jan 12 13:46:39 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Jan 12 13:47:32 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -19,7 +19,7 @@
             (_input
                 (_file "source/src/top.v" + "Top:"
                     (_format verilog)
-                    (_timespec "2024-01-12T13:44:54")
+                    (_timespec "2024-01-12T13:47:07")
                 )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
@@ -223,17 +223,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-01-12T13:46:35")
+                    (_timespec "2024-01-12T13:47:11")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-01-12T13:46:33")
+                    (_timespec "2024-01-12T13:47:10")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-01-12T13:46:35")
+                    (_timespec "2024-01-12T13:47:12")
                 )
             )
         )
@@ -243,13 +243,27 @@
     )
     (_task tsk_synthesis
         (_command cmd_synthesize
-            (_gci_state (_integer 1))
+            (_gci_state (_integer 2))
             (_option ads (_switch ON))
             (_option selected_syn_tool_opt (_integer 2))
+            (_db_output
+                (_file "synthesize/Top_syn.adf"
+                    (_format adif)
+                    (_timespec "2024-01-12T13:47:30")
+                )
+            )
             (_output
+                (_file "synthesize/Top_syn.vm"
+                    (_format structural_verilog)
+                    (_timespec "2024-01-12T13:47:31")
+                )
+                (_file "synthesize/Top.snr"
+                    (_format text)
+                    (_timespec "2024-01-12T13:47:32")
+                )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2024-01-12T13:46:39")
+                    (_timespec "2024-01-12T13:47:32")
                 )
             )
         )
diff --git a/source/src/top.v b/source/src/top.v
index 0d5b367..3329112 100644
--- a/source/src/top.v
+++ b/source/src/top.v
@@ -335,10 +335,10 @@ module Top (
       .timecode_headphone_in(timecode_headphone_in),
 
       //output
-      .timecode_tigger_sig(ISIG_timecode_frame_sync_internal),
-      .timecode_format(ISIGBUS32_timecode_format_internal),  //[31:0] 
-      .timecode_data(ISIGBUS64_timecode_data_internal),  //[63:0]
-      .timecode_serial_data(ISIG_timecode_serial_data_internal),
+      .timecode_tigger_sig(ISIG_timecode_frame_sync_ext),
+      .timecode_format(ISIGBUS32_timecode_format_ext),  //[31:0] 
+      .timecode_data(ISIGBUS64_timecode_data_ext),  //[63:0]
+      .timecode_serial_data(ISIG_timecode_serial_data_ext),
       .timecode_headphone_in_state_led(timecode_headphone_in_state_led),
       .timecode_bnc_in_state_led(timecode_bnc_in_state_led)
   );