6 changed files with 502 additions and 113 deletions
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142led_test.pds
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193source/src/timecode/timecode_decoder.v
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53source/src/timecode/timecode_sample_sig_generator.v
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113source/src/timecode_input.v
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30source/src/top.v
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84source/test/test_timecode_decoder.v
@ -0,0 +1,193 @@ |
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module timecode_decoder #( |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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input timecode_in, |
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output timecode_in_state, |
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|
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|
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/******************************************************************************* |
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* TIMECODE输出 * |
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*******************************************************************************/ |
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output reg timecode_tigger_sig, |
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output reg [63:0] timecode_data, |
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// output [31:0] timecode_format, |
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output timecode_serial_data |
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); |
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|
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// Rate 1/2Fe 1Fe |
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// 23.98 F/s 260.7 us 521.4 us |
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// 24.00 F/s 260.4 us 520.8 us |
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// 25.00 F/s 250.0 us 500.0 us |
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// 29.97 F/s 208.5 us 417.1 us |
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// 30.00 F/s 208.3 us 416.7 us |
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|
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// 260->520 -->130 |
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// 208->416 -->104 |
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// ---> 117us 351us |
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// |
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// 由于TIMECODE的频率范围是固定的，所以这里采用117,和351作为其采样点，这样既可以采样23.98也可以采样30.00 |
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// 对应的采样频率为1000000/117=8547HZ |
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// |
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|
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// 原始数据输出 |
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assign timecode_serial_data = timecode_in; |
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assign timecode_in_state = timecode_in; |
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|
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wire timecode_sample_sig_generator_rest_sig; |
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wire timecode_in_edge; |
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assign timecode_sample_sig_generator_rest_sig = !timecode_in_edge & rst_n; |
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zutils_edge_detecter _signal_in ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(timecode_in), |
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.in_signal_edge(timecode_in_edge) |
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); |
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wire sample_sig; |
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timecode_sample_sig_generator #( |
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
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.SAMPLE_RATE(854700) |
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) timecode_sample_sig_generator ( |
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.clk(clk), |
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.rst_n(timecode_sample_sig_generator_rest_sig), |
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.sample_sig(sample_sig) |
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); |
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|
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|
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// 采样+缓存采样数据 |
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reg [159:0] timecode_data_cache; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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timecode_data_cache <= 0; |
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end else begin |
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if (sample_sig) begin |
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timecode_data_cache <= {timecode_in,timecode_data_cache[159:1]}; |
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end else begin |
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timecode_data_cache <= timecode_data_cache; |
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end |
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end |
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end |
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|
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//译码 |
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reg [79:0] timecode_bit_cache; |
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// integer i; |
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always @(*) begin |
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// for (i = 0; i < 79; i = i + 1) begin |
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// timecode_bit_cache[i] = timecode_data_cache[i*2] & !timecode_data_cache[i*2+1]; |
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// end |
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|
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timecode_bit_cache[0] = timecode_data_cache[0] ^ timecode_data_cache[1]; |
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timecode_bit_cache[1] = timecode_data_cache[2] ^ timecode_data_cache[3]; |
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timecode_bit_cache[2] = timecode_data_cache[4] ^ timecode_data_cache[5]; |
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timecode_bit_cache[3] = timecode_data_cache[6] ^ timecode_data_cache[7]; |
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timecode_bit_cache[4] = timecode_data_cache[8] ^ timecode_data_cache[9]; |
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timecode_bit_cache[5] = timecode_data_cache[10] ^ timecode_data_cache[11]; |
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timecode_bit_cache[6] = timecode_data_cache[12] ^ timecode_data_cache[13]; |
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timecode_bit_cache[7] = timecode_data_cache[14] ^ timecode_data_cache[15]; |
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timecode_bit_cache[8] = timecode_data_cache[16] ^ timecode_data_cache[17]; |
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timecode_bit_cache[9] = timecode_data_cache[18] ^ timecode_data_cache[19]; |
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timecode_bit_cache[10] = timecode_data_cache[20] ^ timecode_data_cache[21]; |
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timecode_bit_cache[11] = timecode_data_cache[22] ^ timecode_data_cache[23]; |
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timecode_bit_cache[12] = timecode_data_cache[24] ^ timecode_data_cache[25]; |
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timecode_bit_cache[13] = timecode_data_cache[26] ^ timecode_data_cache[27]; |
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timecode_bit_cache[14] = timecode_data_cache[28] ^ timecode_data_cache[29]; |
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timecode_bit_cache[15] = timecode_data_cache[30] ^ timecode_data_cache[31]; |
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timecode_bit_cache[16] = timecode_data_cache[32] ^ timecode_data_cache[33]; |
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timecode_bit_cache[17] = timecode_data_cache[34] ^ timecode_data_cache[35]; |
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timecode_bit_cache[18] = timecode_data_cache[36] ^ timecode_data_cache[37]; |
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timecode_bit_cache[19] = timecode_data_cache[38] ^ timecode_data_cache[39]; |
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timecode_bit_cache[20] = timecode_data_cache[40] ^ timecode_data_cache[41]; |
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timecode_bit_cache[21] = timecode_data_cache[42] ^ timecode_data_cache[43]; |
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timecode_bit_cache[22] = timecode_data_cache[44] ^ timecode_data_cache[45]; |
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timecode_bit_cache[23] = timecode_data_cache[46] ^ timecode_data_cache[47]; |
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timecode_bit_cache[24] = timecode_data_cache[48] ^ timecode_data_cache[49]; |
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timecode_bit_cache[25] = timecode_data_cache[50] ^ timecode_data_cache[51]; |
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timecode_bit_cache[26] = timecode_data_cache[52] ^ timecode_data_cache[53]; |
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timecode_bit_cache[27] = timecode_data_cache[54] ^ timecode_data_cache[55]; |
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timecode_bit_cache[28] = timecode_data_cache[56] ^ timecode_data_cache[57]; |
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timecode_bit_cache[29] = timecode_data_cache[58] ^ timecode_data_cache[59]; |
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timecode_bit_cache[30] = timecode_data_cache[60] ^ timecode_data_cache[61]; |
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timecode_bit_cache[31] = timecode_data_cache[62] ^ timecode_data_cache[63]; |
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timecode_bit_cache[32] = timecode_data_cache[64] ^ timecode_data_cache[65]; |
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timecode_bit_cache[33] = timecode_data_cache[66] ^ timecode_data_cache[67]; |
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timecode_bit_cache[34] = timecode_data_cache[68] ^ timecode_data_cache[69]; |
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timecode_bit_cache[35] = timecode_data_cache[70] ^ timecode_data_cache[71]; |
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timecode_bit_cache[36] = timecode_data_cache[72] ^ timecode_data_cache[73]; |
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timecode_bit_cache[37] = timecode_data_cache[74] ^ timecode_data_cache[75]; |
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timecode_bit_cache[38] = timecode_data_cache[76] ^ timecode_data_cache[77]; |
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timecode_bit_cache[39] = timecode_data_cache[78] ^ timecode_data_cache[79]; |
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timecode_bit_cache[40] = timecode_data_cache[80] ^ timecode_data_cache[81]; |
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timecode_bit_cache[41] = timecode_data_cache[82] ^ timecode_data_cache[83]; |
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timecode_bit_cache[42] = timecode_data_cache[84] ^ timecode_data_cache[85]; |
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timecode_bit_cache[43] = timecode_data_cache[86] ^ timecode_data_cache[87]; |
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timecode_bit_cache[44] = timecode_data_cache[88] ^ timecode_data_cache[89]; |
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timecode_bit_cache[45] = timecode_data_cache[90] ^ timecode_data_cache[91]; |
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timecode_bit_cache[46] = timecode_data_cache[92] ^ timecode_data_cache[93]; |
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timecode_bit_cache[47] = timecode_data_cache[94] ^ timecode_data_cache[95]; |
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timecode_bit_cache[48] = timecode_data_cache[96] ^ timecode_data_cache[97]; |
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timecode_bit_cache[49] = timecode_data_cache[98] ^ timecode_data_cache[99]; |
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timecode_bit_cache[50] = timecode_data_cache[100] ^ timecode_data_cache[101]; |
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timecode_bit_cache[51] = timecode_data_cache[102] ^ timecode_data_cache[103]; |
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timecode_bit_cache[52] = timecode_data_cache[104] ^ timecode_data_cache[105]; |
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timecode_bit_cache[53] = timecode_data_cache[106] ^ timecode_data_cache[107]; |
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timecode_bit_cache[54] = timecode_data_cache[108] ^ timecode_data_cache[109]; |
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timecode_bit_cache[55] = timecode_data_cache[110] ^ timecode_data_cache[111]; |
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timecode_bit_cache[56] = timecode_data_cache[112] ^ timecode_data_cache[113]; |
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timecode_bit_cache[57] = timecode_data_cache[114] ^ timecode_data_cache[115]; |
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timecode_bit_cache[58] = timecode_data_cache[116] ^ timecode_data_cache[117]; |
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timecode_bit_cache[59] = timecode_data_cache[118] ^ timecode_data_cache[119]; |
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timecode_bit_cache[60] = timecode_data_cache[120] ^ timecode_data_cache[121]; |
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timecode_bit_cache[61] = timecode_data_cache[122] ^ timecode_data_cache[123]; |
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timecode_bit_cache[62] = timecode_data_cache[124] ^ timecode_data_cache[125]; |
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timecode_bit_cache[63] = timecode_data_cache[126] ^ timecode_data_cache[127]; |
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timecode_bit_cache[64] = timecode_data_cache[128] ^ timecode_data_cache[129]; |
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timecode_bit_cache[65] = timecode_data_cache[130] ^ timecode_data_cache[131]; |
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timecode_bit_cache[66] = timecode_data_cache[132] ^ timecode_data_cache[133]; |
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timecode_bit_cache[67] = timecode_data_cache[134] ^ timecode_data_cache[135]; |
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timecode_bit_cache[68] = timecode_data_cache[136] ^ timecode_data_cache[137]; |
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timecode_bit_cache[69] = timecode_data_cache[138] ^ timecode_data_cache[139]; |
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timecode_bit_cache[70] = timecode_data_cache[140] ^ timecode_data_cache[141]; |
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timecode_bit_cache[71] = timecode_data_cache[142] ^ timecode_data_cache[143]; |
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timecode_bit_cache[72] = timecode_data_cache[144] ^ timecode_data_cache[145]; |
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timecode_bit_cache[73] = timecode_data_cache[146] ^ timecode_data_cache[147]; |
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timecode_bit_cache[74] = timecode_data_cache[148] ^ timecode_data_cache[149]; |
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timecode_bit_cache[75] = timecode_data_cache[150] ^ timecode_data_cache[151]; |
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timecode_bit_cache[76] = timecode_data_cache[152] ^ timecode_data_cache[153]; |
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timecode_bit_cache[77] = timecode_data_cache[154] ^ timecode_data_cache[155]; |
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timecode_bit_cache[78] = timecode_data_cache[156] ^ timecode_data_cache[157]; |
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timecode_bit_cache[79] = timecode_data_cache[158] ^ timecode_data_cache[159]; |
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end |
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|
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// 识别信号捕获 |
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wire [15:0] synccode; |
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assign synccode = timecode_bit_cache[79:64]; |
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assign detect_sync_code = (synccode == 16'b1011_1111_1111_1100); |
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|
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|
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wire detect_sync_code_sig; |
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zutils_edge_detecter detect_sync_code_detect ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(detect_sync_code), |
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.in_signal_rising_edge(detect_sync_code_sig) |
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); |
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|
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//输出时码识别信号 |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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timecode_tigger_sig <= 0; |
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timecode_data <= 0; |
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end else begin |
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if (detect_sync_code_sig) begin |
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timecode_tigger_sig <= 1; |
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timecode_data <= timecode_bit_cache[63:0]; |
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end else begin |
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timecode_tigger_sig <= 0; |
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end |
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end |
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end |
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|
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endmodule |
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@ -0,0 +1,53 @@ |
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module timecode_sample_sig_generator #( |
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parameter SYS_CLOCK_FREQ = 10000000, |
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parameter SAMPLE_RATE = 8547 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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output reg sample_sig |
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); |
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|
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|
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// |
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// sampleSig ______|____________|____________|____________| |
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// |
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|
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localparam COUNT = (SYS_CLOCK_FREQ * 100) / SAMPLE_RATE; |
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reg [31:0] counter; |
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reg [1:0] sub_counter; |
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|
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wire counter_clear; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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counter <= 0; |
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sub_counter <= 1; |
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end else begin |
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|
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if (counter == COUNT) begin |
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counter <= 0; |
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|
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if (sub_counter == 1) begin |
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sample_sig <= 1; |
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sub_counter <= 0; |
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end else begin |
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sub_counter <= 1; |
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end |
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|
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end else begin |
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counter <= counter + 1; |
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sample_sig <= 0; |
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end |
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|
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end |
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end |
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|
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|
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endmodule |
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@ -0,0 +1,113 @@ |
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module timecode_input_parser #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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//寄存器读写接口 |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output wire [31:0] rd_data, |
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|
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input timecode_bnc_in, |
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input timecode_headphone_in, |
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|
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/******************************************************************************* |
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* TIMECODE输出 * |
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*******************************************************************************/ |
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output timecode_tigger_sig, |
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output [31:0] timecode_format, |
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output [63:0] timecode_data, |
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output timecode_serial_data, |
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|
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/******************************************************************************* |
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* 指示灯状态输出 * |
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*******************************************************************************/ |
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output timecode_headphone_in_state_led, |
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output timecode_bnc_in_state_led |
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|
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); |
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|
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|
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reg [31:0] r0_timecode_sig_selt; //信号源选择 0:off,1:bnc,2:headphone |
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reg [31:0] r1_timecode_format; // |
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reg [31:0] r2_timecode0; // |
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reg [31:0] r3_timecode1; // |
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wire [31:0] reg_wr_index; |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.addr(addr), |
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.wr_data(wr_data), |
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.wr_en(wr_en), |
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.rd_data(rd_data), |
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|
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.reg0(r0_timecode_sig_selt), |
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.reg1(r1_timecode_format), |
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.reg2(r2_timecode0), |
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.reg3(r3_timecode1), |
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|
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r0_timecode_sig_selt <= 0; |
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r1_timecode_format <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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31'h0: r0_timecode_sig_selt <= wr_data; |
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31'h1: r1_timecode_format <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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|
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wire timecode_in_af_selt; |
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zutils_multiplexer_4t1 _signal_select ( |
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.chooseindex(r0_timecode_sig_selt), |
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.signal0(1'b0), |
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.signal1(timecode_bnc_in), |
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.signal2(timecode_headphone_in), |
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.signalout(timecode_in_af_selt) |
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); |
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|
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timecode_decoder #( |
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.SYS_CLOCK_FREQ(10000000) |
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) timecode_decoder_ins ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.timecode_in(timecode_in_af_selt), // 时码输入 |
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.timecode_tigger_sig(timecode_tigger_sig), // |
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.timecode_data(timecode_data), //[63:0] |
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.timecode_serial_data(timecode_serial_data) // |
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); |
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|
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|
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r2_timecode0 <= 0; |
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r3_timecode1 <= 0; |
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end else begin |
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if (timecode_tigger_sig) begin |
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r2_timecode0 <= timecode_data[31:0]; |
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r3_timecode1 <= timecode_data[63:32]; |
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end |
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end |
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end |
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|
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assign timecode_format = r1_timecode_format; |
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assign timecode_headphone_in_state_led = 1; |
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assign timecode_bnc_in_state_led = 1; |
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|
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|
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endmodule |
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@ -0,0 +1,84 @@ |
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`timescale 10ns / 10ns |
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module test_timecode_decoder; |
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reg sys_clk; |
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reg rst_n; |
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|
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reg timecode_in; |
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|
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reg one_timecode_end; |
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reg datanow; |
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|
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wire timecode_in_state; |
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wire timecode_tigger_sig; |
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wire [63:0] timecode_data; |
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wire timecode_serial_data; |
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reg [7:0] offset; |
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|
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timecode_decoder #( |
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.SYS_CLOCK_FREQ(10000000) |
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) timecode_decoder_inst ( |
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.clk (sys_clk), |
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.rst_n(rst_n), |
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|
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.timecode_in(timecode_in), |
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.timecode_in_state(timecode_in_state), |
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|
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.timecode_tigger_sig(timecode_tigger_sig), |
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.timecode_data(timecode_data), |
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.timecode_serial_data(timecode_serial_data) |
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); |
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|
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|
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// 250us |
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task timecode_generator; |
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input [79:0] data; |
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integer i; |
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begin |
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for (i = 0; i < 80; i = i + 1) begin |
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offset = i; |
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if (data[i]) begin |
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datanow = 1; |
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end else begin |
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datanow = 0; |
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end |
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timecode_in = ~timecode_in; |
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#25000; |
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if (data[i]) begin |
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timecode_in = ~timecode_in; |
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end |
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#25000; |
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end |
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end |
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endtask |
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|
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initial begin |
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sys_clk = 0; |
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rst_n = 0; |
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#100; |
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rst_n = 1; |
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timecode_in = 0; |
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one_timecode_end = 0; |
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#100; |
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|
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// |
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// timecode_generator(79'h1234_4321_1234_4321_CFFB); |
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// timecode_generator(79'h0000_0000_0000_0000_CFFB); |
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timecode_generator(80'hBFFC_0000_0000_0000_0000); |
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// timecode_generator(79'b1011_1111_1111_1100_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000); |
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//FFFF |
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//4444 |
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//16+16+16+16+16 |
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// 32 32 80 |
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// |
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|
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// timecode_generator(79'hBFFC_0000_0000_0000_0000); |
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// timecode_generator(79'hBFFC_0000_0000_0000_0000); |
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one_timecode_end = 1; |
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#1000000; |
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timecode_generator(80'hBFFC_0102_0304_0506_0102); |
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|
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#100000000; |
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$stop; |
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end |
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always #5 sys_clk = ~sys_clk; // 50MHZ时钟 |
|||
endmodule |
|||
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