11 changed files with 1500 additions and 113 deletions
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2ipcore/inclkpll/.last_generated
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17ipcore/inclkpll/generate.log
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651ipcore/inclkpll/inclkpll.idf
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295ipcore/inclkpll/inclkpll.v
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252ipcore/inclkpll/inclkpll_tb.v
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13ipcore/inclkpll/inclkpll_tmpl.v
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23ipcore/inclkpll/inclkpll_tmpl.vhdl
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178led_test.fdc
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128led_test.pds
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18source/src/monitor_line.v
-
36source/src/top.v
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2023-12-14 21:34 |
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rev_1 |
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IP Generator (Version 2021.1-SP7 build 86875) |
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Check out license ... |
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Start generating at 2023-12-14 21:34 |
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Instance: inclkpll (D:\workspace\fpga_demo\led_test\ipcore\inclkpll\inclkpll.idf) |
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IP: PLL (1.5) |
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Part: Logos-PGL22G-MBG324--6 |
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Create directory 'rtl' ... |
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Copy 'ipml_pll_wrapper_v1_4.v.xml' ... |
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Compile file 'ipml_pll_wrapper_v1_4.v.xml' to 'inclkpll.v' ... |
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Found top module 'inclkpll' in file 'inclkpll.v'. |
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Copy 'ipml_pll_wrapper_v1_4_tb.v.xml' ... |
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Compile file 'ipml_pll_wrapper_v1_4_tb.v.xml' to 'inclkpll_tb.v' ... |
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Create template file 'inclkpll_tmpl.v' ... |
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Create template file 'inclkpll_tmpl.vhdl' ... |
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There is 1 source file to synthesize. |
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Synthesis is disabled. |
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Done: 0 error(s), 0 warning(s) |
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<?xml version="1.0" encoding="UTF-8"?> |
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<ip_inst> |
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<header> |
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<vendor>Pango</vendor> |
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<id>021001</id> |
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<display_name>PLL</display_name> |
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<name>Logos PLL</name> |
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<version>1.5</version> |
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<instance>inclkpll</instance> |
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<family>Logos</family> |
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<device>PGL22G</device> |
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<package>MBG324</package> |
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<speedgrade>-6</speedgrade> |
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<generator version="2021.1-SP7" build="86875">IP Compiler</generator> |
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</header> |
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<param_list> |
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<param> |
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<name>STATIC_PHASE1_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>BANDWIDTH_basicPage</name> |
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<value>OPTIMIZED</value> |
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</param> |
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<param> |
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<name>FBDIV_SEL_advancedPage</name> |
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<value>0</value> |
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</param> |
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<param> |
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<name>CLKOUT4_GATE_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_DUTY1_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_RATIOF_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_DUTY2_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>STATIC_PHASE2_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>DYNAMIC_LOOP_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT2_REQ_PHASE_basicPage</name> |
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<value>0.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>CLK_CAS1_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT1_REQ_DUTY_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>CLKOUT1_REQ_FREQ_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>CLKOUT2_GATE_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>MODE</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_DUTY3_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT1_GATE_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT4_GATE_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_RATIO2_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>STATIC_RATIO1_basicPage</name> |
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<value>12</value> |
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</param> |
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<param> |
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<name>PLL_PWD_ENABLE_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DEVICE_PGL12</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT0_EN_advancedPage</name> |
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<value>true</value> |
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</param> |
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<param> |
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<name>CLKOUT3_REQ_PHASE_basicPage</name> |
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<value>0.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>PLL_PWD_ENABLE_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>RST_ENABLE_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_CLKIN_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_PHASE4_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKOUT1_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_RATIO3_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_RATIOM_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT1_GATE_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_PHASE0_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>FEEDBACK_DELAY_ENABLE_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_DUTY0_basicPage</name> |
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<value>120</value> |
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</param> |
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<param> |
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<name>CLKIN_SEL_EN_ENABLE_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>FBDIV_SEL_basicPage</name> |
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<value>0</value> |
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</param> |
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<param> |
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<name>CLKOUT2_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>FBMODE_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>BANDWIDTH_advancedPage</name> |
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<value>OPTIMIZED</value> |
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</param> |
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<param> |
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<name>STATIC_DUTY0_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>STATIC_DUTY3_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKOUT4_REQ_PHASE_basicPage</name> |
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<value>0.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>DYNAMIC_PHASE3_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT0_REQ_FREQ_basicPage</name> |
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<value>5.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>CLKIN_FREQ_advancedPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>DYNAMIC_PHASE4_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_PHASE4_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>STATIC_RATIO1_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>STATIC_RATIO2_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>DYNAMIC_PHASE0_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLK_CAS4_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_RATIO0_basicPage</name> |
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<value>120</value> |
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</param> |
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<param> |
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<name>CLKOUT0_EXT_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_PHASE1_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_PHASE2_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>FEEDBACK_DELAY_VALUE_basicPage</name> |
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<value>0.000</value> |
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<decimal>3</decimal> |
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</param> |
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<param> |
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<name>DYNAMIC_RATIO1_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT2_GATE_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT3_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLK_CAS1_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKSWITCH_FLAG_ENABLE_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_RATIOF_basicPage</name> |
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<value>24</value> |
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</param> |
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<param> |
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<name>STATIC_PHASE0_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKOUT2_REQ_DUTY_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>CLKOUT4_REQ_DUTY_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>CLKIN_SEL_EN_ENABLE_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_RATIO0_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT0_EXT_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT5_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DEVICE_PGL35</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_DUTY2_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKOUT3_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKIN_BYPASS_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT0_EXT_GATE_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT0_EXT_GATE_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_RATIOI_basicPage</name> |
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<value>2</value> |
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</param> |
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<param> |
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<name>CLKSWITCH_FLAG_ENABLE_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT4_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT4_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT3_REQ_DUTY_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>STATIC_DUTY1_basicPage</name> |
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<value>12</value> |
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</param> |
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<param> |
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<name>CLKOUT0_REQ_PHASE_basicPage</name> |
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<value>0.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>RST_ENABLE_advancedPage</name> |
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<value>true</value> |
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</param> |
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<param> |
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<name>DYNAMIC_DUTY0_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_RATIOM_basicPage</name> |
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<value>1</value> |
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</param> |
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<param> |
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<name>CLK_CAS3_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_DUTY4_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKIN_SEL_ENABLE_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_DUTY4_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>DYNAMIC_RATIO2_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_RATIO3_basicPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLK_CAS2_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT3_REQ_FREQ_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>DYNAMIC_RATIO4_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_RATIO4_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKOUT3_GATE_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT5_GATE_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT4_REQ_FREQ_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>STATIC_RATIO0_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKOUT0_REQ_DUTY_basicPage</name> |
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<value>50.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>CLKOUT0_EN_basicPage</name> |
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<value>true</value> |
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</param> |
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<param> |
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<name>CLKOUT5_SEL_advancedPage</name> |
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<value>0</value> |
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</param> |
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<param> |
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<name>VCODIV2_ENABLE_advancedPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKIN_BYPASS_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT3_GATE_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>STATIC_PHASE3_basicPage</name> |
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<value>16</value> |
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</param> |
|||
<param> |
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<name>CLKOUT1_REQ_PHASE_basicPage</name> |
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<value>0.0000</value> |
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<decimal>4</decimal> |
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</param> |
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<param> |
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<name>STATIC_RATIOF_advancedPage</name> |
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<value>16</value> |
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</param> |
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<param> |
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<name>CLKOUT1_EN_basicPage</name> |
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<value>false</value> |
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</param> |
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<param> |
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<name>CLKOUT0_GATE_EN_advancedPage</name> |
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<value>false</value> |
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</param> |
|||
<param> |
|||
<name>STATIC_DUTYF_basicPage</name> |
|||
<value>24</value> |
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</param> |
|||
<param> |
|||
<name>STATIC_PHASE3_advancedPage</name> |
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<value>16</value> |
|||
</param> |
|||
<param> |
|||
<name>CLKOUT0_GATE_EN_basicPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_RATIOM_advancedPage</name> |
|||
<value>1</value> |
|||
</param> |
|||
<param> |
|||
<name>CLKIN_FREQ_basicPage</name> |
|||
<value>50.0000</value> |
|||
<decimal>4</decimal> |
|||
</param> |
|||
<param> |
|||
<name>PFDEN_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>CLKIN_SEL_ENABLE_basicPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_RATIOI_advancedPage</name> |
|||
<value>2</value> |
|||
</param> |
|||
<param> |
|||
<name>FBMODE_basicPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_PHASE1_advancedPage</name> |
|||
<value>16</value> |
|||
</param> |
|||
<param> |
|||
<name>DYNAMIC_PHASE2_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>DEVICE_PGL22</name> |
|||
<value>true</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_DUTY3_advancedPage</name> |
|||
<value>16</value> |
|||
</param> |
|||
<param> |
|||
<name>LOOP_MAPPING_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>SHOW_SETTING_EN_basicPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>CLK_CAS2_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_DUTY4_advancedPage</name> |
|||
<value>16</value> |
|||
</param> |
|||
<param> |
|||
<name>CLKOUT2_REQ_FREQ_basicPage</name> |
|||
<value>50.0000</value> |
|||
<decimal>4</decimal> |
|||
</param> |
|||
<param> |
|||
<name>MODE_CFG</name> |
|||
<value>0</value> |
|||
</param> |
|||
<param> |
|||
<name>RSTODIV_ENABLE_advancedPage</name> |
|||
<value>true</value> |
|||
</param> |
|||
<param> |
|||
<name>CLKOUT2_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>CLK_CAS4_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_RATIO4_basicPage</name> |
|||
<value>16</value> |
|||
</param> |
|||
<param> |
|||
<name>FEEDBACK_DELAY_VALUE_advancedPage</name> |
|||
<value>0.000</value> |
|||
<decimal>3</decimal> |
|||
</param> |
|||
<param> |
|||
<name>FB_MODE_basicPage</name> |
|||
<value>0</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_DUTY1_advancedPage</name> |
|||
<value>16</value> |
|||
</param> |
|||
<param> |
|||
<name>FB_MODE_advancedPage</name> |
|||
<value>0</value> |
|||
</param> |
|||
<param> |
|||
<name>DYNAMIC_RATIOI_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>CLK_CAS3_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>DYNAMIC_PHASE_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>DYNAMIC_DUTY2_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>STATIC_RATIO3_advancedPage</name> |
|||
<value>16</value> |
|||
</param> |
|||
<param> |
|||
<name>FEEDBACK_DELAY_ENABLE_basicPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
<param> |
|||
<name>DYNAMIC_CLKIN_EN_advancedPage</name> |
|||
<value>false</value> |
|||
</param> |
|||
</param_list> |
|||
<pin_list> |
|||
<pin> |
|||
<name>clkin1</name> |
|||
<text>clkin1</text> |
|||
<dir>input</dir> |
|||
<pos>left</pos> |
|||
</pin> |
|||
<pin> |
|||
<name>pll_lock</name> |
|||
<text>pll_lock</text> |
|||
<dir>output</dir> |
|||
<pos>right</pos> |
|||
</pin> |
|||
<pin> |
|||
<name>clkout0</name> |
|||
<text>clkout0</text> |
|||
<dir>output</dir> |
|||
<pos>right</pos> |
|||
</pin> |
|||
</pin_list> |
|||
<synthesis> |
|||
<script><![CDATA[set_option -vlog_std v2001]]></script> |
|||
<script><![CDATA[set_option -disable_io_insertion 1]]></script> |
|||
</synthesis> |
|||
<file_list> |
|||
<output> |
|||
<file pathname="generate.log" format="log" description="Generate Log"/> |
|||
<file pathname="inclkpll_tmpl.v" format="verilog" description="Instantiation Template"/> |
|||
<file pathname="inclkpll_tmpl.vhdl" format="vhdl" description="Instantiation Template"/> |
|||
</output> |
|||
<source> |
|||
<file pathname="inclkpll.v"/> |
|||
</source> |
|||
</file_list> |
|||
</ip_inst> |
|||
@ -0,0 +1,295 @@ |
|||
// Created by IP Generator (Version 2021.1-SP7 build 86875) |
|||
|
|||
|
|||
|
|||
////////////////////////////////////////////////////////////////////////////// |
|||
// |
|||
// Copyright (c) 2019 PANGO MICROSYSTEMS, INC |
|||
// ALL RIGHTS REVERVED. |
|||
// |
|||
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC. |
|||
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY |
|||
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER. |
|||
// |
|||
////////////////////////////////////////////////////////////////////////////// |
|||
// |
|||
// Library: |
|||
// Filename:inclkpll.v |
|||
////////////////////////////////////////////////////////////////////////////// |
|||
|
|||
module inclkpll ( |
|||
clkin1, |
|||
clkout0, |
|||
|
|||
pll_lock |
|||
); |
|||
|
|||
localparam real CLKIN_FREQ = 50.0; |
|||
localparam integer STATIC_RATIOI = 2; |
|||
localparam integer STATIC_RATIO0 = 120; |
|||
localparam integer STATIC_RATIO1 = 12; |
|||
localparam integer STATIC_RATIO2 = 16; |
|||
localparam integer STATIC_RATIO3 = 16; |
|||
localparam integer STATIC_RATIO4 = 16; |
|||
localparam integer STATIC_RATIOF = 24; |
|||
localparam integer STATIC_DUTY0 = 120; |
|||
localparam integer STATIC_DUTY1 = 12; |
|||
localparam integer STATIC_DUTY2 = 16; |
|||
localparam integer STATIC_DUTY3 = 16; |
|||
localparam integer STATIC_DUTY4 = 16; |
|||
localparam integer STATIC_DUTYF = 24; |
|||
localparam integer STATIC_PHASE0 = 16; |
|||
localparam integer STATIC_PHASE1 = 16; |
|||
localparam integer STATIC_PHASE2 = 16; |
|||
localparam integer STATIC_PHASE3 = 16; |
|||
localparam integer STATIC_PHASE4 = 16; |
|||
localparam CLK_CAS1_EN = "FALSE"; |
|||
localparam CLK_CAS2_EN = "FALSE"; |
|||
localparam CLK_CAS3_EN = "FALSE"; |
|||
localparam CLK_CAS4_EN = "FALSE"; |
|||
localparam CLKIN_BYPASS_EN = "FALSE"; |
|||
localparam CLKOUT0_GATE_EN = "FALSE"; |
|||
localparam CLKOUT0_EXT_GATE_EN = "FALSE"; |
|||
localparam CLKOUT1_GATE_EN = "FALSE"; |
|||
localparam CLKOUT2_GATE_EN = "FALSE"; |
|||
localparam CLKOUT3_GATE_EN = "FALSE"; |
|||
localparam CLKOUT4_GATE_EN = "FALSE"; |
|||
localparam FBMODE = "FALSE"; |
|||
localparam integer FBDIV_SEL = 0; |
|||
localparam BANDWIDTH = "OPTIMIZED"; |
|||
localparam PFDEN_EN = "FALSE"; |
|||
localparam VCOCLK_DIV2 = 1'b0; |
|||
localparam DYNAMIC_RATIOI_EN = "FALSE"; |
|||
localparam DYNAMIC_RATIO0_EN = "FALSE"; |
|||
localparam DYNAMIC_RATIO1_EN = "FALSE"; |
|||
localparam DYNAMIC_RATIO2_EN = "FALSE"; |
|||
localparam DYNAMIC_RATIO3_EN = "FALSE"; |
|||
localparam DYNAMIC_RATIO4_EN = "FALSE"; |
|||
localparam DYNAMIC_RATIOF_EN = "FALSE"; |
|||
localparam DYNAMIC_DUTY0_EN = "FALSE"; |
|||
localparam DYNAMIC_DUTY1_EN = "FALSE"; |
|||
localparam DYNAMIC_DUTY2_EN = "FALSE"; |
|||
localparam DYNAMIC_DUTY3_EN = "FALSE"; |
|||
localparam DYNAMIC_DUTY4_EN = "FALSE"; |
|||
localparam DYNAMIC_DUTYF_EN = "FALSE"; |
|||
localparam PHASE_ADJUST0_EN = "TRUE"; |
|||
localparam PHASE_ADJUST1_EN = (CLK_CAS1_EN == "TRUE") ? "FALSE" : "TRUE"; |
|||
localparam PHASE_ADJUST2_EN = (CLK_CAS2_EN == "TRUE") ? "FALSE" : "TRUE"; |
|||
localparam PHASE_ADJUST3_EN = (CLK_CAS3_EN == "TRUE") ? "FALSE" : "TRUE"; |
|||
localparam PHASE_ADJUST4_EN = (CLK_CAS4_EN == "TRUE") ? "FALSE" : "TRUE"; |
|||
localparam DYNAMIC_PHASE0_EN = "FALSE"; |
|||
localparam DYNAMIC_PHASE1_EN = "FALSE"; |
|||
localparam DYNAMIC_PHASE2_EN = "FALSE"; |
|||
localparam DYNAMIC_PHASE3_EN = "FALSE"; |
|||
localparam DYNAMIC_PHASE4_EN = "FALSE"; |
|||
localparam DYNAMIC_PHASEF_EN = "FALSE"; |
|||
localparam integer STATIC_PHASEF = 16; |
|||
localparam CLK_CAS0_EN = "FALSE"; |
|||
localparam integer CLKOUT5_SEL = 0; |
|||
localparam CLKOUT5_GATE_EN = "FALSE"; |
|||
localparam INTERNAL_FB = (FBMODE == "FALSE") ? "ENABLE":"DISABLE"; |
|||
localparam EXTERNAL_FB = (FBMODE == "FALSE") ? "DISABLE": |
|||
(FBDIV_SEL == 0) ? "CLKOUT0": |
|||
(FBDIV_SEL == 1) ? "CLKOUT1": |
|||
(FBDIV_SEL == 2) ? "CLKOUT2": |
|||
(FBDIV_SEL == 3) ? "CLKOUT3": |
|||
(FBDIV_SEL == 4) ? "CLKOUT4":"DISABLE"; |
|||
localparam RSTODIV_ENABLE = "FALSE"; |
|||
localparam SIM_DEVICE = "PGL22G"; |
|||
|
|||
input clkin1; |
|||
output clkout0; |
|||
|
|||
output pll_lock; |
|||
|
|||
wire clkout0; |
|||
wire clkout0_2pad; |
|||
wire clkout1; |
|||
wire clkout2; |
|||
wire clkout3; |
|||
wire clkout4; |
|||
wire clkout5; |
|||
wire clkswitch_flag; |
|||
wire pll_lock; |
|||
wire clkin1; |
|||
wire clkin2; |
|||
wire clkfb; |
|||
wire clkin_sel; |
|||
wire clkin_sel_en; |
|||
wire pfden; |
|||
wire clkout0_gate; |
|||
wire clkout0_2pad_gate; |
|||
wire clkout1_gate; |
|||
wire clkout2_gate; |
|||
wire clkout3_gate; |
|||
wire clkout4_gate; |
|||
wire clkout5_gate; |
|||
wire [9:0] dyn_idiv; |
|||
wire [9:0] dyn_odiv0; |
|||
wire [9:0] dyn_odiv1; |
|||
wire [9:0] dyn_odiv2; |
|||
wire [9:0] dyn_odiv3; |
|||
wire [9:0] dyn_odiv4; |
|||
wire [9:0] dyn_fdiv; |
|||
wire [9:0] dyn_duty0; |
|||
wire [9:0] dyn_duty1; |
|||
wire [9:0] dyn_duty2; |
|||
wire [9:0] dyn_duty3; |
|||
wire [9:0] dyn_duty4; |
|||
wire [12:0] dyn_phase0; |
|||
wire [12:0] dyn_phase1; |
|||
wire [12:0] dyn_phase2; |
|||
wire [12:0] dyn_phase3; |
|||
wire [12:0] dyn_phase4; |
|||
wire pll_pwd; |
|||
wire pll_rst; |
|||
wire rstodiv; |
|||
wire icp_base; |
|||
wire [3:0] icp_sel; |
|||
wire [2:0] lpfres_sel; |
|||
wire cripple_sel; |
|||
wire [2:0] phase_sel; |
|||
wire phase_dir; |
|||
wire phase_step_n; |
|||
wire load_phase; |
|||
wire [6:0] dyn_mdiv; |
|||
|
|||
assign clkin2 = 1'b0; |
|||
assign clkin_sel = 1'b0; |
|||
assign clkin_sel_en = 1'b0; |
|||
|
|||
assign pll_pwd = 1'b0; |
|||
|
|||
assign pll_rst = 1'b0; |
|||
|
|||
assign rstodiv = 1'b0; |
|||
|
|||
GTP_PLL_E1 #( |
|||
.CLKIN_FREQ(CLKIN_FREQ), |
|||
.PFDEN_EN(PFDEN_EN), |
|||
.VCOCLK_DIV2(VCOCLK_DIV2), |
|||
.DYNAMIC_RATIOI_EN(DYNAMIC_RATIOI_EN), |
|||
|
|||
.DYNAMIC_RATIO0_EN(DYNAMIC_RATIO0_EN), |
|||
.DYNAMIC_RATIO1_EN(DYNAMIC_RATIO1_EN), |
|||
.DYNAMIC_RATIO2_EN(DYNAMIC_RATIO2_EN), |
|||
.DYNAMIC_RATIO3_EN(DYNAMIC_RATIO3_EN), |
|||
.DYNAMIC_RATIO4_EN(DYNAMIC_RATIO4_EN), |
|||
.DYNAMIC_RATIOF_EN(DYNAMIC_RATIOF_EN), |
|||
.STATIC_RATIOI(STATIC_RATIOI), |
|||
|
|||
.STATIC_RATIO0(STATIC_RATIO0), |
|||
.STATIC_RATIO1(STATIC_RATIO1), |
|||
.STATIC_RATIO2(STATIC_RATIO2), |
|||
.STATIC_RATIO3(STATIC_RATIO3), |
|||
.STATIC_RATIO4(STATIC_RATIO4), |
|||
.STATIC_RATIOF(STATIC_RATIOF), |
|||
.DYNAMIC_DUTY0_EN(DYNAMIC_DUTY0_EN), |
|||
.DYNAMIC_DUTY1_EN(DYNAMIC_DUTY1_EN), |
|||
.DYNAMIC_DUTY2_EN(DYNAMIC_DUTY2_EN), |
|||
.DYNAMIC_DUTY3_EN(DYNAMIC_DUTY3_EN), |
|||
.DYNAMIC_DUTY4_EN(DYNAMIC_DUTY4_EN), |
|||
.DYNAMIC_DUTYF_EN(DYNAMIC_DUTYF_EN), |
|||
.STATIC_DUTY0(STATIC_DUTY0), |
|||
.STATIC_DUTY1(STATIC_DUTY1), |
|||
.STATIC_DUTY2(STATIC_DUTY2), |
|||
.STATIC_DUTY3(STATIC_DUTY3), |
|||
.STATIC_DUTY4(STATIC_DUTY4), |
|||
.STATIC_DUTYF(STATIC_DUTYF), |
|||
.PHASE_ADJUST0_EN(PHASE_ADJUST0_EN), |
|||
.PHASE_ADJUST1_EN(PHASE_ADJUST1_EN), |
|||
.PHASE_ADJUST2_EN(PHASE_ADJUST2_EN), |
|||
.PHASE_ADJUST3_EN(PHASE_ADJUST3_EN), |
|||
.PHASE_ADJUST4_EN(PHASE_ADJUST4_EN), |
|||
.DYNAMIC_PHASE0_EN(DYNAMIC_PHASE0_EN), |
|||
.DYNAMIC_PHASE1_EN(DYNAMIC_PHASE1_EN), |
|||
.DYNAMIC_PHASE2_EN(DYNAMIC_PHASE2_EN), |
|||
.DYNAMIC_PHASE3_EN(DYNAMIC_PHASE3_EN), |
|||
.DYNAMIC_PHASE4_EN(DYNAMIC_PHASE4_EN), |
|||
.DYNAMIC_PHASEF_EN(DYNAMIC_PHASEF_EN), |
|||
.STATIC_PHASE0(STATIC_PHASE0[2:0]), |
|||
.STATIC_PHASE1(STATIC_PHASE1[2:0]), |
|||
.STATIC_PHASE2(STATIC_PHASE2[2:0]), |
|||
.STATIC_PHASE3(STATIC_PHASE3[2:0]), |
|||
.STATIC_PHASE4(STATIC_PHASE4[2:0]), |
|||
.STATIC_PHASEF(STATIC_PHASEF[2:0]), |
|||
.STATIC_CPHASE0(STATIC_PHASE0[12:3]), |
|||
.STATIC_CPHASE1(STATIC_PHASE1[12:3]), |
|||
.STATIC_CPHASE2(STATIC_PHASE2[12:3]), |
|||
.STATIC_CPHASE3(STATIC_PHASE3[12:3]), |
|||
.STATIC_CPHASE4(STATIC_PHASE4[12:3]), |
|||
.STATIC_CPHASEF(STATIC_PHASEF[12:3]), |
|||
.CLK_CAS0_EN(CLK_CAS0_EN), |
|||
.CLK_CAS1_EN(CLK_CAS1_EN), |
|||
.CLK_CAS2_EN(CLK_CAS2_EN), |
|||
.CLK_CAS3_EN(CLK_CAS3_EN), |
|||
.CLK_CAS4_EN(CLK_CAS4_EN), |
|||
.CLKOUT5_SEL(CLKOUT5_SEL), |
|||
.CLKIN_BYPASS_EN(CLKIN_BYPASS_EN), |
|||
.CLKOUT0_SYN_EN(CLKOUT0_GATE_EN), |
|||
.CLKOUT0_EXT_SYN_EN(CLKOUT0_EXT_GATE_EN), |
|||
.CLKOUT1_SYN_EN(CLKOUT1_GATE_EN), |
|||
.CLKOUT2_SYN_EN(CLKOUT2_GATE_EN), |
|||
.CLKOUT3_SYN_EN(CLKOUT3_GATE_EN), |
|||
.CLKOUT4_SYN_EN(CLKOUT4_GATE_EN), |
|||
.CLKOUT5_SYN_EN(CLKOUT5_GATE_EN), |
|||
.INTERNAL_FB(INTERNAL_FB), |
|||
.EXTERNAL_FB(EXTERNAL_FB), |
|||
.RSTODIV_PHASE_EN(RSTODIV_ENABLE), |
|||
.SIM_DEVICE(SIM_DEVICE), |
|||
.BANDWIDTH(BANDWIDTH) |
|||
) u_pll_e1 ( |
|||
.CLKOUT0(clkout0), |
|||
.CLKOUT0_EXT(clkout0_2pad), |
|||
.CLKOUT1(clkout1), |
|||
.CLKOUT2(clkout2), |
|||
.CLKOUT3(clkout3), |
|||
.CLKOUT4(clkout4), |
|||
.CLKOUT5(clkout5), |
|||
.CLKSWITCH_FLAG(clkswitch_flag), |
|||
.LOCK(pll_lock), |
|||
.CLKIN1(clkin1), |
|||
.CLKIN2(clkin2), |
|||
.CLKFB(clkfb), |
|||
.CLKIN_SEL(clkin_sel), |
|||
.CLKIN_SEL_EN(clkin_sel_en), |
|||
.PFDEN(pfden), |
|||
|
|||
.RATIOI(dyn_idiv), |
|||
.RATIO0(dyn_odiv0), |
|||
.RATIO1(dyn_odiv1), |
|||
.RATIO2(dyn_odiv2), |
|||
.RATIO3(dyn_odiv3), |
|||
.RATIO4(dyn_odiv4), |
|||
.RATIOF(dyn_fdiv), |
|||
.DUTY0(dyn_duty0), |
|||
.DUTY1(dyn_duty1), |
|||
.DUTY2(dyn_duty2), |
|||
.DUTY3(dyn_duty3), |
|||
.DUTY4(dyn_duty4), |
|||
.DUTYF(), |
|||
.PHASE0(dyn_phase0[2:0]), |
|||
.PHASE1(dyn_phase1[2:0]), |
|||
.PHASE2(dyn_phase2[2:0]), |
|||
.PHASE3(dyn_phase3[2:0]), |
|||
.PHASE4(dyn_phase4[2:0]), |
|||
.PHASEF(), |
|||
.CPHASE0(dyn_phase0[12:3]), |
|||
.CPHASE1(dyn_phase1[12:3]), |
|||
.CPHASE2(dyn_phase2[12:3]), |
|||
.CPHASE3(dyn_phase3[12:3]), |
|||
.CPHASE4(dyn_phase4[12:3]), |
|||
.CPHASEF(), |
|||
.CLKOUT0_SYN(clkout0_gate), |
|||
.CLKOUT0_EXT_SYN(clkout0_2pad_gate), |
|||
.CLKOUT1_SYN(clkout1_gate), |
|||
.CLKOUT2_SYN(clkout2_gate), |
|||
.CLKOUT3_SYN(clkout3_gate), |
|||
.CLKOUT4_SYN(clkout4_gate), |
|||
.CLKOUT5_SYN(clkout5_gate), |
|||
.PLL_PWD(pll_pwd), |
|||
.RST(pll_rst), |
|||
.RSTODIV_PHASE(rstodiv) |
|||
); |
|||
|
|||
endmodule |
|||
@ -0,0 +1,252 @@ |
|||
// Created by IP Generator (Version 2021.1-SP7 build 86875) |
|||
|
|||
|
|||
|
|||
////////////////////////////////////////////////////////////////////////////// |
|||
// |
|||
// Copyright (c) 2019 PANGO MICROSYSTEMS, INC |
|||
// ALL RIGHTS REVERVED. |
|||
// |
|||
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC. |
|||
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY |
|||
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER. |
|||
// |
|||
////////////////////////////////////////////////////////////////////////////// |
|||
// |
|||
// Library: |
|||
// Filename:inclkpll.v |
|||
////////////////////////////////////////////////////////////////////////////// |
|||
`timescale 1 ns/1 ps |
|||
|
|||
module inclkpll_tb (); |
|||
|
|||
localparam CLKIN_FREQ = 50.0; |
|||
localparam integer FBDIV_SEL = 0; |
|||
localparam FBMODE = "FALSE"; |
|||
|
|||
|
|||
// Generate testbench reset and clock |
|||
reg pll_rst; |
|||
reg rstodiv; |
|||
reg pll_pwd; |
|||
reg clkin1; |
|||
reg clkin2; |
|||
reg clkin_dsel; |
|||
reg clkin_dsel_en; |
|||
reg pfden; |
|||
reg clkout0_gate; |
|||
reg clkout0_2pad_gate; |
|||
reg clkout1_gate; |
|||
reg clkout2_gate; |
|||
reg clkout3_gate; |
|||
reg clkout4_gate; |
|||
reg clkout5_gate; |
|||
reg [9:0] dyn_idiv; |
|||
reg [9:0] dyn_odiv0; |
|||
reg [9:0] dyn_odiv1; |
|||
reg [9:0] dyn_odiv2; |
|||
reg [9:0] dyn_odiv3; |
|||
reg [9:0] dyn_odiv4; |
|||
reg [9:0] dyn_fdiv; |
|||
reg [9:0] dyn_duty0; |
|||
reg [9:0] dyn_duty1; |
|||
reg [9:0] dyn_duty2; |
|||
reg [9:0] dyn_duty3; |
|||
reg [9:0] dyn_duty4; |
|||
reg [12:0] dyn_phase0; |
|||
reg [12:0] dyn_phase1; |
|||
reg [12:0] dyn_phase2; |
|||
reg [12:0] dyn_phase3; |
|||
reg [12:0] dyn_phase4; |
|||
reg err_chk; |
|||
reg [2:0] results_cnt; |
|||
|
|||
reg rst_n; |
|||
reg clk_tb; |
|||
|
|||
wire clkout0; |
|||
wire clkout1; |
|||
wire clkout2; |
|||
wire clkout3; |
|||
wire clkout4; |
|||
wire clkfb = (FBMODE == "FALSE") ? clkin1 : |
|||
(FBDIV_SEL == 0 ) ? clkout0 : |
|||
(FBDIV_SEL == 1 ) ? clkout1 : |
|||
(FBDIV_SEL == 2 ) ? clkout2 : |
|||
(FBDIV_SEL == 3 ) ? clkout3 : |
|||
(FBDIV_SEL == 4 ) ? clkout4 : clkin1; |
|||
|
|||
|
|||
initial |
|||
begin |
|||
rst_n = 0; |
|||
#20 |
|||
rst_n = 1; |
|||
end |
|||
|
|||
initial |
|||
begin |
|||
clk_tb = 0; |
|||
forever #1 clk_tb = ~clk_tb; |
|||
end |
|||
|
|||
parameter CLOCK_PERIOD1 = (500.0/CLKIN_FREQ); |
|||
//parameter CLOCK_PERIOD2 = (500.0/CLKIN_FREQ); |
|||
|
|||
initial |
|||
begin |
|||
clkin1 = 0; |
|||
forever #(CLOCK_PERIOD1) clkin1 = ~clkin1; |
|||
end |
|||
|
|||
|
|||
initial |
|||
begin |
|||
pll_pwd = 0; |
|||
pll_rst = 0; |
|||
rstodiv = 0; |
|||
clkin_dsel = 0; |
|||
clkin_dsel_en = 0; |
|||
pfden = 0; |
|||
clkout0_gate = 0; |
|||
clkout0_2pad_gate = 0; |
|||
clkout1_gate = 0; |
|||
clkout2_gate = 0; |
|||
clkout3_gate = 0; |
|||
clkout4_gate = 0; |
|||
clkout5_gate = 0; |
|||
dyn_idiv = 10'd2; |
|||
dyn_fdiv = 10'd32; |
|||
dyn_odiv0 = 10'd100; |
|||
dyn_odiv1 = 10'd100; |
|||
dyn_odiv2 = 10'd100; |
|||
dyn_odiv3 = 10'd100; |
|||
dyn_odiv4 = 10'd100; |
|||
dyn_duty0 = 10'd100; |
|||
dyn_duty1 = 10'd100; |
|||
dyn_duty2 = 10'd100; |
|||
dyn_duty3 = 10'd100; |
|||
dyn_duty4 = 10'd100; |
|||
dyn_phase0 = 13'd16; |
|||
dyn_phase1 = 13'd16; |
|||
dyn_phase2 = 13'd16; |
|||
dyn_phase3 = 13'd16; |
|||
dyn_phase4 = 13'd16; |
|||
|
|||
#10 |
|||
pll_pwd = 1; |
|||
#20 |
|||
pll_pwd = 0; |
|||
|
|||
pll_rst = 0; |
|||
#10 |
|||
pll_rst = 1; |
|||
#20 |
|||
pll_rst = 0; |
|||
|
|||
#1000000 |
|||
dyn_odiv0 = 10'd200; |
|||
dyn_odiv1 = 10'd200; |
|||
dyn_odiv2 = 10'd200; |
|||
dyn_odiv3 = 10'd200; |
|||
dyn_odiv4 = 10'd200; |
|||
dyn_duty0 = 10'd200; |
|||
dyn_duty1 = 10'd200; |
|||
dyn_duty2 = 10'd200; |
|||
dyn_duty3 = 10'd200; |
|||
dyn_duty4 = 10'd200; |
|||
#3000000 |
|||
$finish; |
|||
end |
|||
|
|||
initial |
|||
begin |
|||
$display("Simulation Starts.") ; |
|||
$display("Simulation is done.") ; |
|||
if (|results_cnt) |
|||
$display("Simulation Failed due to Error Found.") ; |
|||
else |
|||
$display("Simulation Success.") ; |
|||
end |
|||
|
|||
|
|||
GTP_GRS GRS_INST( |
|||
.GRS_N(1'b1) |
|||
); |
|||
|
|||
inclkpll U_inclkpll ( |
|||
.clkout0(clkout0), |
|||
|
|||
.clkin1(clkin1), |
|||
|
|||
.pll_lock(pll_lock) |
|||
); |
|||
|
|||
|
|||
//******************Results Cheching************************ |
|||
|
|||
reg [2:0] pll_lock_shift; |
|||
wire pll_lock_pulse = ~pll_lock_shift[2] & pll_lock_shift[1]; |
|||
always @( posedge clk_tb or negedge rst_n ) |
|||
begin |
|||
if (!rst_n) |
|||
begin |
|||
pll_lock_shift <= 3'd0; |
|||
end |
|||
else |
|||
begin |
|||
pll_lock_shift[0] <= pll_lock; |
|||
pll_lock_shift[2:1] <= pll_lock_shift[1:0]; |
|||
end |
|||
end |
|||
|
|||
reg [1:0] pll_lock_pulse_cnt; |
|||
always @( posedge clk_tb or negedge rst_n ) |
|||
begin |
|||
if (!rst_n) |
|||
begin |
|||
pll_lock_pulse_cnt <= 2'd0; |
|||
end |
|||
else |
|||
begin |
|||
if (pll_lock_pulse) |
|||
pll_lock_pulse_cnt <= pll_lock_pulse_cnt + 1; |
|||
else ; |
|||
end |
|||
end |
|||
|
|||
|
|||
always @( posedge clk_tb or negedge rst_n ) |
|||
begin |
|||
if (!rst_n) |
|||
begin |
|||
err_chk <= 1'b0; |
|||
end |
|||
else |
|||
begin |
|||
if ((!pll_lock) && (^pll_lock_pulse_cnt)) |
|||
err_chk <= 1'b1; |
|||
else if (pll_lock_pulse_cnt[1]) |
|||
err_chk <= 1'b1; |
|||
else |
|||
err_chk <= 1'b0; |
|||
end |
|||
end |
|||
always @(posedge clk_tb or negedge rst_n) |
|||
begin |
|||
if (!rst_n) |
|||
results_cnt <= 3'b000 ; |
|||
else if (&results_cnt) |
|||
results_cnt <= 3'b100 ; |
|||
else if (err_chk) |
|||
results_cnt <= results_cnt + 3'd1 ; |
|||
end |
|||
|
|||
|
|||
integer result_fid; |
|||
initial begin |
|||
result_fid = $fopen ("sim_results.log","a"); |
|||
$fmonitor(result_fid,"err_chk=%b", err_chk); |
|||
end |
|||
|
|||
endmodule |
|||
@ -0,0 +1,13 @@ |
|||
// Created by IP Generator (Version 2021.1-SP7 build 86875) |
|||
// Instantiation Template |
|||
// |
|||
// Insert the following codes into your Verilog file. |
|||
// * Change the_instance_name to your own instance name. |
|||
// * Change the signal names in the port associations |
|||
|
|||
|
|||
inclkpll the_instance_name ( |
|||
.clkin1(clkin1), // input |
|||
.pll_lock(pll_lock), // output |
|||
.clkout0(clkout0) // output |
|||
); |
|||
@ -0,0 +1,23 @@ |
|||
-- Created by IP Generator (Version 2021.1-SP7 build 86875) |
|||
-- Instantiation Template |
|||
-- |
|||
-- Insert the following codes into your VHDL file. |
|||
-- * Change the_instance_name to your own instance name. |
|||
-- * Change the net names in the port map. |
|||
|
|||
|
|||
COMPONENT inclkpll |
|||
PORT ( |
|||
clkin1 : IN STD_LOGIC; |
|||
pll_lock : OUT STD_LOGIC; |
|||
clkout0 : OUT STD_LOGIC |
|||
); |
|||
END COMPONENT; |
|||
|
|||
|
|||
the_instance_name : inclkpll |
|||
PORT MAP ( |
|||
clkin1 => clkin1, |
|||
pll_lock => pll_lock, |
|||
clkout0 => clkout0 |
|||
); |
|||
@ -0,0 +1,18 @@ |
|||
/* |
|||
* Hacky baud rate generator to divide a 50MHz clock into a 115200 baud |
|||
* rx/tx pair where the rx clcken oversamples by 16x. |
|||
*/ |
|||
module monitor_line ( |
|||
input wire clk_50m, |
|||
input wire rst_n, |
|||
input wire in, |
|||
output reg out |
|||
); |
|||
|
|||
|
|||
always @(posedge clk_50m or negedge rst_n) begin |
|||
if (!rst_n) out <= 1'b0; |
|||
else out <= in; |
|||
end |
|||
|
|||
endmodule |
|||
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