diff --git a/ipcore/inclkpll/.last_generated b/ipcore/inclkpll/.last_generated new file mode 100644 index 0000000..ffefb81 --- /dev/null +++ b/ipcore/inclkpll/.last_generated @@ -0,0 +1,2 @@ +2023-12-14 21:34 +rev_1 \ No newline at end of file diff --git a/ipcore/inclkpll/generate.log b/ipcore/inclkpll/generate.log new file mode 100644 index 0000000..219b3d8 --- /dev/null +++ b/ipcore/inclkpll/generate.log @@ -0,0 +1,17 @@ +IP Generator (Version 2021.1-SP7 build 86875) +Check out license ... +Start generating at 2023-12-14 21:34 +Instance: inclkpll (D:\workspace\fpga_demo\led_test\ipcore\inclkpll\inclkpll.idf) +IP: PLL (1.5) +Part: Logos-PGL22G-MBG324--6 +Create directory 'rtl' ... +Copy 'ipml_pll_wrapper_v1_4.v.xml' ... +Compile file 'ipml_pll_wrapper_v1_4.v.xml' to 'inclkpll.v' ... +Found top module 'inclkpll' in file 'inclkpll.v'. +Copy 'ipml_pll_wrapper_v1_4_tb.v.xml' ... +Compile file 'ipml_pll_wrapper_v1_4_tb.v.xml' to 'inclkpll_tb.v' ... +Create template file 'inclkpll_tmpl.v' ... +Create template file 'inclkpll_tmpl.vhdl' ... +There is 1 source file to synthesize. +Synthesis is disabled. +Done: 0 error(s), 0 warning(s) diff --git a/ipcore/inclkpll/inclkpll.idf b/ipcore/inclkpll/inclkpll.idf new file mode 100644 index 0000000..4a491ac --- /dev/null +++ b/ipcore/inclkpll/inclkpll.idf @@ -0,0 +1,651 @@ + + +
+ Pango + 021001 + PLL + Logos PLL + 1.5 + inclkpll + Logos + PGL22G + MBG324 + -6 + IP Compiler +
+ + + STATIC_PHASE1_basicPage + 16 + + + BANDWIDTH_basicPage + OPTIMIZED + + + FBDIV_SEL_advancedPage + 0 + + + CLKOUT4_GATE_EN_advancedPage + false + + + DYNAMIC_DUTY1_EN_advancedPage + false + + + DYNAMIC_RATIOF_EN_advancedPage + false + + + STATIC_DUTY2_advancedPage + 16 + + + STATIC_PHASE2_advancedPage + 16 + + + DYNAMIC_LOOP_EN_advancedPage + false + + + CLKOUT2_REQ_PHASE_basicPage + 0.0000 + 4 + + + CLK_CAS1_EN_basicPage + false + + + CLKOUT1_REQ_DUTY_basicPage + 50.0000 + 4 + + + CLKOUT1_REQ_FREQ_basicPage + 50.0000 + 4 + + + CLKOUT2_GATE_EN_basicPage + false + + + MODE + false + + + DYNAMIC_DUTY3_EN_advancedPage + false + + + CLKOUT1_GATE_EN_advancedPage + false + + + CLKOUT4_GATE_EN_basicPage + false + + + STATIC_RATIO2_advancedPage + 16 + + + STATIC_RATIO1_basicPage + 12 + + + PLL_PWD_ENABLE_basicPage + false + + + DEVICE_PGL12 + false + + + CLKOUT0_EN_advancedPage + true + + + CLKOUT3_REQ_PHASE_basicPage + 0.0000 + 4 + + + PLL_PWD_ENABLE_advancedPage + false + + + RST_ENABLE_basicPage + false + + + DYNAMIC_CLKIN_EN_basicPage + false + + + STATIC_PHASE4_basicPage + 16 + + + CLKOUT1_EN_advancedPage + false + + + DYNAMIC_RATIO3_EN_advancedPage + false + + + DYNAMIC_RATIOM_EN_advancedPage + false + + + CLKOUT1_GATE_EN_basicPage + false + + + STATIC_PHASE0_advancedPage + 16 + + + FEEDBACK_DELAY_ENABLE_advancedPage + false + + + STATIC_DUTY0_basicPage + 120 + + + CLKIN_SEL_EN_ENABLE_basicPage + false + + + FBDIV_SEL_basicPage + 0 + + + CLKOUT2_EN_basicPage + false + + + FBMODE_advancedPage + false + + + BANDWIDTH_advancedPage + OPTIMIZED + + + STATIC_DUTY0_advancedPage + 16 + + + STATIC_DUTY3_basicPage + 16 + + + CLKOUT4_REQ_PHASE_basicPage + 0.0000 + 4 + + + DYNAMIC_PHASE3_EN_advancedPage + false + + + CLKOUT0_REQ_FREQ_basicPage + 5.0000 + 4 + + + CLKIN_FREQ_advancedPage + 50.0000 + 4 + + + DYNAMIC_PHASE4_EN_advancedPage + false + + + STATIC_PHASE4_advancedPage + 16 + + + STATIC_RATIO1_advancedPage + 16 + + + STATIC_RATIO2_basicPage + 16 + + + DYNAMIC_PHASE0_EN_advancedPage + false + + + CLK_CAS4_EN_basicPage + false + + + STATIC_RATIO0_basicPage + 120 + + + CLKOUT0_EXT_EN_basicPage + false + + + DYNAMIC_PHASE1_EN_advancedPage + false + + + STATIC_PHASE2_basicPage + 16 + + + FEEDBACK_DELAY_VALUE_basicPage + 0.000 + 3 + + + DYNAMIC_RATIO1_EN_advancedPage + false + + + CLKOUT2_GATE_EN_advancedPage + false + + + CLKOUT3_EN_basicPage + false + + + CLK_CAS1_EN_advancedPage + false + + + CLKSWITCH_FLAG_ENABLE_basicPage + false + + + STATIC_RATIOF_basicPage + 24 + + + STATIC_PHASE0_basicPage + 16 + + + CLKOUT2_REQ_DUTY_basicPage + 50.0000 + 4 + + + CLKOUT4_REQ_DUTY_basicPage + 50.0000 + 4 + + + CLKIN_SEL_EN_ENABLE_advancedPage + false + + + DYNAMIC_RATIO0_EN_advancedPage + false + + + CLKOUT0_EXT_EN_advancedPage + false + + + CLKOUT5_EN_advancedPage + false + + + DEVICE_PGL35 + false + + + STATIC_DUTY2_basicPage + 16 + + + CLKOUT3_EN_advancedPage + false + + + CLKIN_BYPASS_EN_advancedPage + false + + + CLKOUT0_EXT_GATE_EN_basicPage + false + + + CLKOUT0_EXT_GATE_EN_advancedPage + false + + + STATIC_RATIOI_basicPage + 2 + + + CLKSWITCH_FLAG_ENABLE_advancedPage + false + + + CLKOUT4_EN_basicPage + false + + + CLKOUT4_EN_advancedPage + false + + + CLKOUT3_REQ_DUTY_basicPage + 50.0000 + 4 + + + STATIC_DUTY1_basicPage + 12 + + + CLKOUT0_REQ_PHASE_basicPage + 0.0000 + 4 + + + RST_ENABLE_advancedPage + true + + + DYNAMIC_DUTY0_EN_advancedPage + false + + + STATIC_RATIOM_basicPage + 1 + + + CLK_CAS3_EN_basicPage + false + + + STATIC_DUTY4_basicPage + 16 + + + CLKIN_SEL_ENABLE_advancedPage + false + + + DYNAMIC_DUTY4_EN_advancedPage + false + + + DYNAMIC_RATIO2_EN_advancedPage + false + + + STATIC_RATIO3_basicPage + 16 + + + CLK_CAS2_EN_basicPage + false + + + CLKOUT3_REQ_FREQ_basicPage + 50.0000 + 4 + + + DYNAMIC_RATIO4_EN_advancedPage + false + + + STATIC_RATIO4_advancedPage + 16 + + + CLKOUT3_GATE_EN_advancedPage + false + + + CLKOUT5_GATE_EN_advancedPage + false + + + CLKOUT4_REQ_FREQ_basicPage + 50.0000 + 4 + + + STATIC_RATIO0_advancedPage + 16 + + + CLKOUT0_REQ_DUTY_basicPage + 50.0000 + 4 + + + CLKOUT0_EN_basicPage + true + + + CLKOUT5_SEL_advancedPage + 0 + + + VCODIV2_ENABLE_advancedPage + false + + + CLKIN_BYPASS_EN_basicPage + false + + + CLKOUT3_GATE_EN_basicPage + false + + + STATIC_PHASE3_basicPage + 16 + + + CLKOUT1_REQ_PHASE_basicPage + 0.0000 + 4 + + + STATIC_RATIOF_advancedPage + 16 + + + CLKOUT1_EN_basicPage + false + + + CLKOUT0_GATE_EN_advancedPage + false + + + STATIC_DUTYF_basicPage + 24 + + + STATIC_PHASE3_advancedPage + 16 + + + CLKOUT0_GATE_EN_basicPage + false + + + STATIC_RATIOM_advancedPage + 1 + + + CLKIN_FREQ_basicPage + 50.0000 + 4 + + + PFDEN_EN_advancedPage + false + + + CLKIN_SEL_ENABLE_basicPage + false + + + STATIC_RATIOI_advancedPage + 2 + + + FBMODE_basicPage + false + + + STATIC_PHASE1_advancedPage + 16 + + + DYNAMIC_PHASE2_EN_advancedPage + false + + + DEVICE_PGL22 + true + + + STATIC_DUTY3_advancedPage + 16 + + + LOOP_MAPPING_EN_advancedPage + false + + + SHOW_SETTING_EN_basicPage + false + + + CLK_CAS2_EN_advancedPage + false + + + STATIC_DUTY4_advancedPage + 16 + + + CLKOUT2_REQ_FREQ_basicPage + 50.0000 + 4 + + + MODE_CFG + 0 + + + RSTODIV_ENABLE_advancedPage + true + + + CLKOUT2_EN_advancedPage + false + + + CLK_CAS4_EN_advancedPage + false + + + STATIC_RATIO4_basicPage + 16 + + + FEEDBACK_DELAY_VALUE_advancedPage + 0.000 + 3 + + + FB_MODE_basicPage + 0 + + + STATIC_DUTY1_advancedPage + 16 + + + FB_MODE_advancedPage + 0 + + + DYNAMIC_RATIOI_EN_advancedPage + false + + + CLK_CAS3_EN_advancedPage + false + + + DYNAMIC_PHASE_EN_advancedPage + false + + + DYNAMIC_DUTY2_EN_advancedPage + false + + + STATIC_RATIO3_advancedPage + 16 + + + FEEDBACK_DELAY_ENABLE_basicPage + false + + + DYNAMIC_CLKIN_EN_advancedPage + false + + + + + clkin1 + clkin1 + input + left + + + pll_lock + pll_lock + output + right + + + clkout0 + clkout0 + output + right + + + + + + + + + + + + + + + + + diff --git a/ipcore/inclkpll/inclkpll.v b/ipcore/inclkpll/inclkpll.v new file mode 100644 index 0000000..90e3baa --- /dev/null +++ b/ipcore/inclkpll/inclkpll.v @@ -0,0 +1,295 @@ +// Created by IP Generator (Version 2021.1-SP7 build 86875) + + + +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2019 PANGO MICROSYSTEMS, INC +// ALL RIGHTS REVERVED. +// +// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC. +// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY +// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER. +// +////////////////////////////////////////////////////////////////////////////// +// +// Library: +// Filename:inclkpll.v +////////////////////////////////////////////////////////////////////////////// + +module inclkpll ( + clkin1, + clkout0, + + pll_lock + ); + + localparam real CLKIN_FREQ = 50.0; + localparam integer STATIC_RATIOI = 2; + localparam integer STATIC_RATIO0 = 120; + localparam integer STATIC_RATIO1 = 12; + localparam integer STATIC_RATIO2 = 16; + localparam integer STATIC_RATIO3 = 16; + localparam integer STATIC_RATIO4 = 16; + localparam integer STATIC_RATIOF = 24; + localparam integer STATIC_DUTY0 = 120; + localparam integer STATIC_DUTY1 = 12; + localparam integer STATIC_DUTY2 = 16; + localparam integer STATIC_DUTY3 = 16; + localparam integer STATIC_DUTY4 = 16; + localparam integer STATIC_DUTYF = 24; + localparam integer STATIC_PHASE0 = 16; + localparam integer STATIC_PHASE1 = 16; + localparam integer STATIC_PHASE2 = 16; + localparam integer STATIC_PHASE3 = 16; + localparam integer STATIC_PHASE4 = 16; + localparam CLK_CAS1_EN = "FALSE"; + localparam CLK_CAS2_EN = "FALSE"; + localparam CLK_CAS3_EN = "FALSE"; + localparam CLK_CAS4_EN = "FALSE"; + localparam CLKIN_BYPASS_EN = "FALSE"; + localparam CLKOUT0_GATE_EN = "FALSE"; + localparam CLKOUT0_EXT_GATE_EN = "FALSE"; + localparam CLKOUT1_GATE_EN = "FALSE"; + localparam CLKOUT2_GATE_EN = "FALSE"; + localparam CLKOUT3_GATE_EN = "FALSE"; + localparam CLKOUT4_GATE_EN = "FALSE"; + localparam FBMODE = "FALSE"; + localparam integer FBDIV_SEL = 0; + localparam BANDWIDTH = "OPTIMIZED"; + localparam PFDEN_EN = "FALSE"; + localparam VCOCLK_DIV2 = 1'b0; + localparam DYNAMIC_RATIOI_EN = "FALSE"; + localparam DYNAMIC_RATIO0_EN = "FALSE"; + localparam DYNAMIC_RATIO1_EN = "FALSE"; + localparam DYNAMIC_RATIO2_EN = "FALSE"; + localparam DYNAMIC_RATIO3_EN = "FALSE"; + localparam DYNAMIC_RATIO4_EN = "FALSE"; + localparam DYNAMIC_RATIOF_EN = "FALSE"; + localparam DYNAMIC_DUTY0_EN = "FALSE"; + localparam DYNAMIC_DUTY1_EN = "FALSE"; + localparam DYNAMIC_DUTY2_EN = "FALSE"; + localparam DYNAMIC_DUTY3_EN = "FALSE"; + localparam DYNAMIC_DUTY4_EN = "FALSE"; + localparam DYNAMIC_DUTYF_EN = "FALSE"; + localparam PHASE_ADJUST0_EN = "TRUE"; + localparam PHASE_ADJUST1_EN = (CLK_CAS1_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam PHASE_ADJUST2_EN = (CLK_CAS2_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam PHASE_ADJUST3_EN = (CLK_CAS3_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam PHASE_ADJUST4_EN = (CLK_CAS4_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam DYNAMIC_PHASE0_EN = "FALSE"; + localparam DYNAMIC_PHASE1_EN = "FALSE"; + localparam DYNAMIC_PHASE2_EN = "FALSE"; + localparam DYNAMIC_PHASE3_EN = "FALSE"; + localparam DYNAMIC_PHASE4_EN = "FALSE"; + localparam DYNAMIC_PHASEF_EN = "FALSE"; + localparam integer STATIC_PHASEF = 16; + localparam CLK_CAS0_EN = "FALSE"; + localparam integer CLKOUT5_SEL = 0; + localparam CLKOUT5_GATE_EN = "FALSE"; + localparam INTERNAL_FB = (FBMODE == "FALSE") ? "ENABLE":"DISABLE"; + localparam EXTERNAL_FB = (FBMODE == "FALSE") ? "DISABLE": + (FBDIV_SEL == 0) ? "CLKOUT0": + (FBDIV_SEL == 1) ? "CLKOUT1": + (FBDIV_SEL == 2) ? "CLKOUT2": + (FBDIV_SEL == 3) ? "CLKOUT3": + (FBDIV_SEL == 4) ? "CLKOUT4":"DISABLE"; + localparam RSTODIV_ENABLE = "FALSE"; + localparam SIM_DEVICE = "PGL22G"; + + input clkin1; + output clkout0; + + output pll_lock; + + wire clkout0; + wire clkout0_2pad; + wire clkout1; + wire clkout2; + wire clkout3; + wire clkout4; + wire clkout5; + wire clkswitch_flag; + wire pll_lock; + wire clkin1; + wire clkin2; + wire clkfb; + wire clkin_sel; + wire clkin_sel_en; + wire pfden; + wire clkout0_gate; + wire clkout0_2pad_gate; + wire clkout1_gate; + wire clkout2_gate; + wire clkout3_gate; + wire clkout4_gate; + wire clkout5_gate; + wire [9:0] dyn_idiv; + wire [9:0] dyn_odiv0; + wire [9:0] dyn_odiv1; + wire [9:0] dyn_odiv2; + wire [9:0] dyn_odiv3; + wire [9:0] dyn_odiv4; + wire [9:0] dyn_fdiv; + wire [9:0] dyn_duty0; + wire [9:0] dyn_duty1; + wire [9:0] dyn_duty2; + wire [9:0] dyn_duty3; + wire [9:0] dyn_duty4; + wire [12:0] dyn_phase0; + wire [12:0] dyn_phase1; + wire [12:0] dyn_phase2; + wire [12:0] dyn_phase3; + wire [12:0] dyn_phase4; + wire pll_pwd; + wire pll_rst; + wire rstodiv; + wire icp_base; + wire [3:0] icp_sel; + wire [2:0] lpfres_sel; + wire cripple_sel; + wire [2:0] phase_sel; + wire phase_dir; + wire phase_step_n; + wire load_phase; + wire [6:0] dyn_mdiv; + + assign clkin2 = 1'b0; + assign clkin_sel = 1'b0; + assign clkin_sel_en = 1'b0; + + assign pll_pwd = 1'b0; + + assign pll_rst = 1'b0; + + assign rstodiv = 1'b0; + +GTP_PLL_E1 #( + .CLKIN_FREQ(CLKIN_FREQ), + .PFDEN_EN(PFDEN_EN), + .VCOCLK_DIV2(VCOCLK_DIV2), + .DYNAMIC_RATIOI_EN(DYNAMIC_RATIOI_EN), + + .DYNAMIC_RATIO0_EN(DYNAMIC_RATIO0_EN), + .DYNAMIC_RATIO1_EN(DYNAMIC_RATIO1_EN), + .DYNAMIC_RATIO2_EN(DYNAMIC_RATIO2_EN), + .DYNAMIC_RATIO3_EN(DYNAMIC_RATIO3_EN), + .DYNAMIC_RATIO4_EN(DYNAMIC_RATIO4_EN), + .DYNAMIC_RATIOF_EN(DYNAMIC_RATIOF_EN), + .STATIC_RATIOI(STATIC_RATIOI), + + .STATIC_RATIO0(STATIC_RATIO0), + .STATIC_RATIO1(STATIC_RATIO1), + .STATIC_RATIO2(STATIC_RATIO2), + .STATIC_RATIO3(STATIC_RATIO3), + .STATIC_RATIO4(STATIC_RATIO4), + .STATIC_RATIOF(STATIC_RATIOF), + .DYNAMIC_DUTY0_EN(DYNAMIC_DUTY0_EN), + .DYNAMIC_DUTY1_EN(DYNAMIC_DUTY1_EN), + .DYNAMIC_DUTY2_EN(DYNAMIC_DUTY2_EN), + .DYNAMIC_DUTY3_EN(DYNAMIC_DUTY3_EN), + .DYNAMIC_DUTY4_EN(DYNAMIC_DUTY4_EN), + .DYNAMIC_DUTYF_EN(DYNAMIC_DUTYF_EN), + .STATIC_DUTY0(STATIC_DUTY0), + .STATIC_DUTY1(STATIC_DUTY1), + .STATIC_DUTY2(STATIC_DUTY2), + .STATIC_DUTY3(STATIC_DUTY3), + .STATIC_DUTY4(STATIC_DUTY4), + .STATIC_DUTYF(STATIC_DUTYF), + .PHASE_ADJUST0_EN(PHASE_ADJUST0_EN), + .PHASE_ADJUST1_EN(PHASE_ADJUST1_EN), + .PHASE_ADJUST2_EN(PHASE_ADJUST2_EN), + .PHASE_ADJUST3_EN(PHASE_ADJUST3_EN), + .PHASE_ADJUST4_EN(PHASE_ADJUST4_EN), + .DYNAMIC_PHASE0_EN(DYNAMIC_PHASE0_EN), + .DYNAMIC_PHASE1_EN(DYNAMIC_PHASE1_EN), + .DYNAMIC_PHASE2_EN(DYNAMIC_PHASE2_EN), + .DYNAMIC_PHASE3_EN(DYNAMIC_PHASE3_EN), + .DYNAMIC_PHASE4_EN(DYNAMIC_PHASE4_EN), + .DYNAMIC_PHASEF_EN(DYNAMIC_PHASEF_EN), + .STATIC_PHASE0(STATIC_PHASE0[2:0]), + .STATIC_PHASE1(STATIC_PHASE1[2:0]), + .STATIC_PHASE2(STATIC_PHASE2[2:0]), + .STATIC_PHASE3(STATIC_PHASE3[2:0]), + .STATIC_PHASE4(STATIC_PHASE4[2:0]), + .STATIC_PHASEF(STATIC_PHASEF[2:0]), + .STATIC_CPHASE0(STATIC_PHASE0[12:3]), + .STATIC_CPHASE1(STATIC_PHASE1[12:3]), + .STATIC_CPHASE2(STATIC_PHASE2[12:3]), + .STATIC_CPHASE3(STATIC_PHASE3[12:3]), + .STATIC_CPHASE4(STATIC_PHASE4[12:3]), + .STATIC_CPHASEF(STATIC_PHASEF[12:3]), + .CLK_CAS0_EN(CLK_CAS0_EN), + .CLK_CAS1_EN(CLK_CAS1_EN), + .CLK_CAS2_EN(CLK_CAS2_EN), + .CLK_CAS3_EN(CLK_CAS3_EN), + .CLK_CAS4_EN(CLK_CAS4_EN), + .CLKOUT5_SEL(CLKOUT5_SEL), + .CLKIN_BYPASS_EN(CLKIN_BYPASS_EN), + .CLKOUT0_SYN_EN(CLKOUT0_GATE_EN), + .CLKOUT0_EXT_SYN_EN(CLKOUT0_EXT_GATE_EN), + .CLKOUT1_SYN_EN(CLKOUT1_GATE_EN), + .CLKOUT2_SYN_EN(CLKOUT2_GATE_EN), + .CLKOUT3_SYN_EN(CLKOUT3_GATE_EN), + .CLKOUT4_SYN_EN(CLKOUT4_GATE_EN), + .CLKOUT5_SYN_EN(CLKOUT5_GATE_EN), + .INTERNAL_FB(INTERNAL_FB), + .EXTERNAL_FB(EXTERNAL_FB), + .RSTODIV_PHASE_EN(RSTODIV_ENABLE), + .SIM_DEVICE(SIM_DEVICE), + .BANDWIDTH(BANDWIDTH) + ) u_pll_e1 ( + .CLKOUT0(clkout0), + .CLKOUT0_EXT(clkout0_2pad), + .CLKOUT1(clkout1), + .CLKOUT2(clkout2), + .CLKOUT3(clkout3), + .CLKOUT4(clkout4), + .CLKOUT5(clkout5), + .CLKSWITCH_FLAG(clkswitch_flag), + .LOCK(pll_lock), + .CLKIN1(clkin1), + .CLKIN2(clkin2), + .CLKFB(clkfb), + .CLKIN_SEL(clkin_sel), + .CLKIN_SEL_EN(clkin_sel_en), + .PFDEN(pfden), + + .RATIOI(dyn_idiv), + .RATIO0(dyn_odiv0), + .RATIO1(dyn_odiv1), + .RATIO2(dyn_odiv2), + .RATIO3(dyn_odiv3), + .RATIO4(dyn_odiv4), + .RATIOF(dyn_fdiv), + .DUTY0(dyn_duty0), + .DUTY1(dyn_duty1), + .DUTY2(dyn_duty2), + .DUTY3(dyn_duty3), + .DUTY4(dyn_duty4), + .DUTYF(), + .PHASE0(dyn_phase0[2:0]), + .PHASE1(dyn_phase1[2:0]), + .PHASE2(dyn_phase2[2:0]), + .PHASE3(dyn_phase3[2:0]), + .PHASE4(dyn_phase4[2:0]), + .PHASEF(), + .CPHASE0(dyn_phase0[12:3]), + .CPHASE1(dyn_phase1[12:3]), + .CPHASE2(dyn_phase2[12:3]), + .CPHASE3(dyn_phase3[12:3]), + .CPHASE4(dyn_phase4[12:3]), + .CPHASEF(), + .CLKOUT0_SYN(clkout0_gate), + .CLKOUT0_EXT_SYN(clkout0_2pad_gate), + .CLKOUT1_SYN(clkout1_gate), + .CLKOUT2_SYN(clkout2_gate), + .CLKOUT3_SYN(clkout3_gate), + .CLKOUT4_SYN(clkout4_gate), + .CLKOUT5_SYN(clkout5_gate), + .PLL_PWD(pll_pwd), + .RST(pll_rst), + .RSTODIV_PHASE(rstodiv) + ); + +endmodule diff --git a/ipcore/inclkpll/inclkpll_tb.v b/ipcore/inclkpll/inclkpll_tb.v new file mode 100644 index 0000000..0c6af5b --- /dev/null +++ b/ipcore/inclkpll/inclkpll_tb.v @@ -0,0 +1,252 @@ +// Created by IP Generator (Version 2021.1-SP7 build 86875) + + + +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2019 PANGO MICROSYSTEMS, INC +// ALL RIGHTS REVERVED. +// +// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC. +// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY +// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER. +// +////////////////////////////////////////////////////////////////////////////// +// +// Library: +// Filename:inclkpll.v +////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ps + +module inclkpll_tb (); + +localparam CLKIN_FREQ = 50.0; +localparam integer FBDIV_SEL = 0; +localparam FBMODE = "FALSE"; + + +// Generate testbench reset and clock +reg pll_rst; +reg rstodiv; +reg pll_pwd; +reg clkin1; +reg clkin2; +reg clkin_dsel; +reg clkin_dsel_en; +reg pfden; +reg clkout0_gate; +reg clkout0_2pad_gate; +reg clkout1_gate; +reg clkout2_gate; +reg clkout3_gate; +reg clkout4_gate; +reg clkout5_gate; +reg [9:0] dyn_idiv; +reg [9:0] dyn_odiv0; +reg [9:0] dyn_odiv1; +reg [9:0] dyn_odiv2; +reg [9:0] dyn_odiv3; +reg [9:0] dyn_odiv4; +reg [9:0] dyn_fdiv; +reg [9:0] dyn_duty0; +reg [9:0] dyn_duty1; +reg [9:0] dyn_duty2; +reg [9:0] dyn_duty3; +reg [9:0] dyn_duty4; +reg [12:0] dyn_phase0; +reg [12:0] dyn_phase1; +reg [12:0] dyn_phase2; +reg [12:0] dyn_phase3; +reg [12:0] dyn_phase4; +reg err_chk; +reg [2:0] results_cnt; + +reg rst_n; +reg clk_tb; + +wire clkout0; +wire clkout1; +wire clkout2; +wire clkout3; +wire clkout4; +wire clkfb = (FBMODE == "FALSE") ? clkin1 : + (FBDIV_SEL == 0 ) ? clkout0 : + (FBDIV_SEL == 1 ) ? clkout1 : + (FBDIV_SEL == 2 ) ? clkout2 : + (FBDIV_SEL == 3 ) ? clkout3 : + (FBDIV_SEL == 4 ) ? clkout4 : clkin1; + + +initial +begin + rst_n = 0; + #20 + rst_n = 1; +end + +initial +begin + clk_tb = 0; + forever #1 clk_tb = ~clk_tb; +end + +parameter CLOCK_PERIOD1 = (500.0/CLKIN_FREQ); +//parameter CLOCK_PERIOD2 = (500.0/CLKIN_FREQ); + +initial +begin + clkin1 = 0; + forever #(CLOCK_PERIOD1) clkin1 = ~clkin1; +end + + +initial +begin + pll_pwd = 0; + pll_rst = 0; + rstodiv = 0; + clkin_dsel = 0; + clkin_dsel_en = 0; + pfden = 0; + clkout0_gate = 0; + clkout0_2pad_gate = 0; + clkout1_gate = 0; + clkout2_gate = 0; + clkout3_gate = 0; + clkout4_gate = 0; + clkout5_gate = 0; + dyn_idiv = 10'd2; + dyn_fdiv = 10'd32; + dyn_odiv0 = 10'd100; + dyn_odiv1 = 10'd100; + dyn_odiv2 = 10'd100; + dyn_odiv3 = 10'd100; + dyn_odiv4 = 10'd100; + dyn_duty0 = 10'd100; + dyn_duty1 = 10'd100; + dyn_duty2 = 10'd100; + dyn_duty3 = 10'd100; + dyn_duty4 = 10'd100; + dyn_phase0 = 13'd16; + dyn_phase1 = 13'd16; + dyn_phase2 = 13'd16; + dyn_phase3 = 13'd16; + dyn_phase4 = 13'd16; + + #10 + pll_pwd = 1; + #20 + pll_pwd = 0; + + pll_rst = 0; + #10 + pll_rst = 1; + #20 + pll_rst = 0; + + #1000000 + dyn_odiv0 = 10'd200; + dyn_odiv1 = 10'd200; + dyn_odiv2 = 10'd200; + dyn_odiv3 = 10'd200; + dyn_odiv4 = 10'd200; + dyn_duty0 = 10'd200; + dyn_duty1 = 10'd200; + dyn_duty2 = 10'd200; + dyn_duty3 = 10'd200; + dyn_duty4 = 10'd200; + #3000000 + $finish; +end + +initial +begin + $display("Simulation Starts.") ; + $display("Simulation is done.") ; + if (|results_cnt) + $display("Simulation Failed due to Error Found.") ; + else + $display("Simulation Success.") ; +end + + +GTP_GRS GRS_INST( + .GRS_N(1'b1) + ); + +inclkpll U_inclkpll ( +.clkout0(clkout0), + + .clkin1(clkin1), + + .pll_lock(pll_lock) + ); + + +//******************Results Cheching************************ + +reg [2:0] pll_lock_shift; +wire pll_lock_pulse = ~pll_lock_shift[2] & pll_lock_shift[1]; +always @( posedge clk_tb or negedge rst_n ) +begin + if (!rst_n) + begin + pll_lock_shift <= 3'd0; + end + else + begin + pll_lock_shift[0] <= pll_lock; + pll_lock_shift[2:1] <= pll_lock_shift[1:0]; + end +end + +reg [1:0] pll_lock_pulse_cnt; +always @( posedge clk_tb or negedge rst_n ) +begin + if (!rst_n) + begin + pll_lock_pulse_cnt <= 2'd0; + end + else + begin + if (pll_lock_pulse) + pll_lock_pulse_cnt <= pll_lock_pulse_cnt + 1; + else ; + end +end + + +always @( posedge clk_tb or negedge rst_n ) +begin + if (!rst_n) + begin + err_chk <= 1'b0; + end + else + begin + if ((!pll_lock) && (^pll_lock_pulse_cnt)) + err_chk <= 1'b1; + else if (pll_lock_pulse_cnt[1]) + err_chk <= 1'b1; + else + err_chk <= 1'b0; + end +end +always @(posedge clk_tb or negedge rst_n) +begin + if (!rst_n) + results_cnt <= 3'b000 ; + else if (&results_cnt) + results_cnt <= 3'b100 ; + else if (err_chk) + results_cnt <= results_cnt + 3'd1 ; +end + + +integer result_fid; +initial begin + result_fid = $fopen ("sim_results.log","a"); + $fmonitor(result_fid,"err_chk=%b", err_chk); +end + +endmodule diff --git a/ipcore/inclkpll/inclkpll_tmpl.v b/ipcore/inclkpll/inclkpll_tmpl.v new file mode 100644 index 0000000..86124ba --- /dev/null +++ b/ipcore/inclkpll/inclkpll_tmpl.v @@ -0,0 +1,13 @@ +// Created by IP Generator (Version 2021.1-SP7 build 86875) +// Instantiation Template +// +// Insert the following codes into your Verilog file. +// * Change the_instance_name to your own instance name. +// * Change the signal names in the port associations + + +inclkpll the_instance_name ( + .clkin1(clkin1), // input + .pll_lock(pll_lock), // output + .clkout0(clkout0) // output +); diff --git a/ipcore/inclkpll/inclkpll_tmpl.vhdl b/ipcore/inclkpll/inclkpll_tmpl.vhdl new file mode 100644 index 0000000..ff1eea5 --- /dev/null +++ b/ipcore/inclkpll/inclkpll_tmpl.vhdl @@ -0,0 +1,23 @@ +-- Created by IP Generator (Version 2021.1-SP7 build 86875) +-- Instantiation Template +-- +-- Insert the following codes into your VHDL file. +-- * Change the_instance_name to your own instance name. +-- * Change the net names in the port map. + + +COMPONENT inclkpll + PORT ( + clkin1 : IN STD_LOGIC; + pll_lock : OUT STD_LOGIC; + clkout0 : OUT STD_LOGIC + ); +END COMPONENT; + + +the_instance_name : inclkpll + PORT MAP ( + clkin1 => clkin1, + pll_lock => pll_lock, + clkout0 => clkout0 + ); diff --git a/led_test.fdc b/led_test.fdc index 45778d1..eaebcfc 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -70,87 +70,97 @@ define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} #define_attribute {p:tx_TxD_start} {PAP_IO_STANDARD} {LVCMOS33} #define_attribute {p:tx_TxD_start} {PAP_IO_DRIVE} {4} #define_attribute {p:tx_TxD_start} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io3} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io3} {PAP_IO_LOC} {T11} -define_attribute {p:test_io3} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io3} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io3} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io3} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io4} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io4} {PAP_IO_LOC} {R11} -define_attribute {p:test_io4} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io4} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io4} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io4} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io5} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io5} {PAP_IO_LOC} {P12} -define_attribute {p:test_io5} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io5} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io5} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io5} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io6} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io6} {PAP_IO_LOC} {P11} -define_attribute {p:test_io6} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io6} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io6} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io6} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io7} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io7} {PAP_IO_LOC} {T13} -define_attribute {p:test_io7} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io7} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io7} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io7} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io8} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io8} {PAP_IO_LOC} {R13} -define_attribute {p:test_io8} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io8} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io8} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io8} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io9} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io9} {PAP_IO_LOC} {P13} -define_attribute {p:test_io9} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io9} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io9} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io9} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io10} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io10} {PAP_IO_LOC} {P14} -define_attribute {p:test_io10} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io10} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io10} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io10} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io11} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io11} {PAP_IO_LOC} {R15} -define_attribute {p:test_io11} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io11} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io11} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io11} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io12} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io12} {PAP_IO_LOC} {R14} -define_attribute {p:test_io12} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io12} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io12} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io12} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io13} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io13} {PAP_IO_LOC} {T16} -define_attribute {p:test_io13} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io13} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io13} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io13} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io14} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io14} {PAP_IO_LOC} {R16} -define_attribute {p:test_io14} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io14} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io14} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io14} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io15} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io15} {PAP_IO_LOC} {U16} -define_attribute {p:test_io15} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io15} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io15} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io15} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io16} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io16} {PAP_IO_LOC} {V16} -define_attribute {p:test_io16} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io16} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io16} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io16} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[3]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[3]} {PAP_IO_LOC} {T11} +define_attribute {p:test_io[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[3]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[3]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[3]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[4]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[4]} {PAP_IO_LOC} {R11} +define_attribute {p:test_io[4]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[4]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[4]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[4]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[5]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[5]} {PAP_IO_LOC} {P12} +define_attribute {p:test_io[5]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[5]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[5]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[5]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[6]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[6]} {PAP_IO_LOC} {P11} +define_attribute {p:test_io[6]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[6]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[6]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[6]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[7]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[7]} {PAP_IO_LOC} {T13} +define_attribute {p:test_io[7]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[7]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[7]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[7]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[8]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[8]} {PAP_IO_LOC} {R13} +define_attribute {p:test_io[8]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[8]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[8]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[8]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[9]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[9]} {PAP_IO_LOC} {P13} +define_attribute {p:test_io[9]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[9]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[9]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[9]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[10]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[10]} {PAP_IO_LOC} {P14} +define_attribute {p:test_io[10]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[10]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[10]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[10]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[11]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[11]} {PAP_IO_LOC} {R15} +define_attribute {p:test_io[11]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[11]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[11]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[11]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[12]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[12]} {PAP_IO_LOC} {R14} +define_attribute {p:test_io[12]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[12]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[12]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[12]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[13]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[13]} {PAP_IO_LOC} {T16} +define_attribute {p:test_io[13]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[13]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[13]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[13]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[14]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[14]} {PAP_IO_LOC} {R16} +define_attribute {p:test_io[14]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[14]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[14]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[14]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[15]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[15]} {PAP_IO_LOC} {U16} +define_attribute {p:test_io[15]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[15]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[15]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[15]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:test_io[16]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:test_io[16]} {PAP_IO_LOC} {V16} +define_attribute {p:test_io[16]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:test_io[16]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:test_io[16]} {PAP_IO_DRIVE} {4} +define_attribute {p:test_io[16]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:usb_serial_tx} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:usb_serial_tx} {PAP_IO_LOC} {C10} +define_attribute {p:usb_serial_tx} {PAP_IO_VCCIO} {3.3} +define_attribute {p:usb_serial_tx} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:usb_serial_tx} {PAP_IO_DRIVE} {4} +define_attribute {p:usb_serial_tx} {PAP_IO_SLEW} {SLOW} +define_attribute {p:usb_serial_rx} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:usb_serial_rx} {PAP_IO_LOC} {A12} +define_attribute {p:usb_serial_rx} {PAP_IO_VCCIO} {3.3} +define_attribute {p:usb_serial_rx} {PAP_IO_STANDARD} {LVTTL33} diff --git a/led_test.pds b/led_test.pds index f284b42..7ee02d4 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Dec 14 20:47:37 2023") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Dec 14 21:56:34 2023") (_version "1.0.5") (_status "initial") (_project @@ -27,7 +27,7 @@ ) (_file "source/src/top.v" + "Top" (_format verilog) - (_timespec "2023-12-14T16:57:50") + (_timespec "2023-12-14T21:43:40") ) (_file "source/src/uart_tx.v" (_format verilog) @@ -41,15 +41,27 @@ (_format verilog) (_timespec "2023-12-14T20:47:29") ) + (_file "source/src/monitor_line.v" + (_format verilog) + (_timespec "2023-12-14T21:44:03") + ) ) ) (_widget wgt_my_ips_src + (_input + (_ip "ipcore/inclkpll/inclkpll.idf" + (_timespec "2023-12-14T21:34:50") + (_ip_source_item "ipcore/inclkpll/inclkpll.v" + (_timespec "2023-12-14T21:34:50") + ) + ) + ) ) (_widget wgt_import_logic_con_file (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2023-12-13T22:49:15") + (_timespec "2023-12-14T21:55:40") ) ) ) @@ -88,17 +100,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2023-12-14T20:47:35") + (_timespec "2023-12-14T21:55:55") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2023-12-14T20:47:35") + (_timespec "2023-12-14T21:55:55") ) (_file "compile/cmr.db" (_format text) - (_timespec "2023-12-14T20:47:35") + (_timespec "2023-12-14T21:55:55") ) ) ) @@ -114,21 +126,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2023-12-14T20:47:37") + (_timespec "2023-12-14T21:55:58") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2023-12-14T20:47:37") + (_timespec "2023-12-14T21:55:58") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2023-12-14T20:47:37") + (_timespec "2023-12-14T21:55:58") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2023-12-14T20:47:37") + (_timespec "2023-12-14T21:55:58") ) ) ) @@ -145,14 +157,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2023-12-14T21:56:00") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2023-12-14T21:56:00") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2023-12-14T21:56:00") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2023-12-14T21:56:00") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2023-12-14T20:10:02") + (_timespec "2023-12-14T21:56:00") ) ) ) @@ -162,7 +194,39 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2023-12-14T21:56:20") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2023-12-14T21:56:20") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2023-12-14T21:56:20") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2023-12-14T21:56:20") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2023-12-14T21:56:14") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2023-12-14T21:56:20") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2023-12-14T21:56:21") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -171,8 +235,24 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_attribute _auto_exe_lock (_switch OFF)) + (_db_output + (_file "report_timing/Top_rtp.adf" + (_format adif) + (_timespec "2023-12-14T21:56:24") + ) + ) + (_output + (_file "report_timing/Top.rtr" + (_format text) + (_timespec "2023-12-14T21:56:24") + ) + (_file "report_timing/rtr.db" + (_format text) + (_timespec "2023-12-14T21:56:25") + ) + ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -190,7 +270,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2023-12-14T21:56:33") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2023-12-14T21:56:33") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2023-12-14T21:56:33") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2023-12-14T21:56:34") + ) + ) ) ) ) diff --git a/source/src/monitor_line.v b/source/src/monitor_line.v new file mode 100644 index 0000000..c71536d --- /dev/null +++ b/source/src/monitor_line.v @@ -0,0 +1,18 @@ +/* + * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud + * rx/tx pair where the rx clcken oversamples by 16x. + */ +module monitor_line ( + input wire clk_50m, + input wire rst_n, + input wire in, + output reg out +); + + + always @(posedge clk_50m or negedge rst_n) begin + if (!rst_n) out <= 1'b0; + else out <= in; + end + +endmodule diff --git a/source/src/top.v b/source/src/top.v index da0d053..d4cecc7 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -3,22 +3,30 @@ module Top ( input sys_clk, input rst_n, output reg [3:0] led, - output wire test_io3, - output wire test_io4, - output wire test_io5, - output wire test_io6, - output wire test_io7, - output wire test_io8, - output wire test_io9, - output wire test_io10, - output wire test_io11, - output wire test_io12, - output wire test_io13, - output wire test_io14, - output wire test_io15, - output wire test_io16 + output reg [3:0] key, + output wire usb_serial_tx, + input wire usb_serial_rx, + output wire [35:3] test_io ); + wire inclkpll_clk0out; + inclkpll inclkpll_inst ( + .clkin1 (sys_clk), + .clkout0(inclkpll_clk0out) + ); + uart_reg_reader uart_reg_reader_impl ( + .clk(sys_clk), + .rst_n(rst_n), + .reg_data(), + .reg_add(), + .reg_add_valid(), + .uart_rx_pin(usb_serial_rx), + .uart_tx_pin(usb_serial_tx) + ); + + monitor_line monitor_line_usb_serial_rx(sys_clk, rst_n, usb_serial_rx, test_io[4]); + assign test_io[3] = usb_serial_tx; +// assign test_io[3] = inclkpll_clk0out; endmodule