From 7d6dcd9818c6c3d5c200bbb4d1d849ccd6f40e67 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Wed, 10 Jan 2024 22:04:31 +0800 Subject: [PATCH] 20240110 --- ipcore/SPLL/.last_generated | 2 +- ipcore/SPLL/SPLL.idf | 500 ++++++++++++++++++++--------------------- ipcore/SPLL/SPLL.v | 10 +- ipcore/SPLL/SPLL_tb.v | 2 +- ipcore/SPLL/generate.log | 2 +- led_test.pds | 38 +--- source/src/output/ttl_output.v | 3 +- source/src/top.v | 27 ++- 8 files changed, 290 insertions(+), 294 deletions(-) diff --git a/ipcore/SPLL/.last_generated b/ipcore/SPLL/.last_generated index 188a96e..ab5d3a1 100644 --- a/ipcore/SPLL/.last_generated +++ b/ipcore/SPLL/.last_generated @@ -1,2 +1,2 @@ -2024-01-07 14:25 +2024-01-10 21:58 rev_1 \ No newline at end of file diff --git a/ipcore/SPLL/SPLL.idf b/ipcore/SPLL/SPLL.idf index cd0dfb5..f266421 100644 --- a/ipcore/SPLL/SPLL.idf +++ b/ipcore/SPLL/SPLL.idf @@ -15,179 +15,179 @@ - CLKOUT4_REQ_PHASE_basicPage - 0.0000 - 4 - - - CLKOUT3_REQ_FREQ_basicPage - 50.0000 - 4 + RST_ENABLE_basicPage + false - STATIC_PHASE4_advancedPage - 16 + CLKOUT0_EXT_EN_advancedPage + false - DYNAMIC_RATIOI_EN_advancedPage + DYNAMIC_PHASE4_EN_advancedPage false - CLKOUT4_EN_basicPage + CLKSWITCH_FLAG_ENABLE_advancedPage false - STATIC_DUTY0_advancedPage - 16 + FB_MODE_basicPage + 0 - STATIC_DUTY3_basicPage - 16 + RST_ENABLE_advancedPage + false - CLKOUT0_GATE_EN_basicPage + CLKOUT5_EN_advancedPage false - CLKIN_SEL_EN_ENABLE_basicPage - false + DEVICE_PGL22 + true - CLKOUT0_EXT_EN_advancedPage - false + CLKOUT3_REQ_FREQ_basicPage + 50.0000 + 4 - DYNAMIC_RATIO0_EN_advancedPage + CLKOUT1_EN_advancedPage false - DYNAMIC_CLKIN_EN_basicPage + CLK_CAS3_EN_advancedPage false - DYNAMIC_RATIOM_EN_advancedPage - false + CLKOUT0_REQ_DUTY_basicPage + 50.0000 + 4 - CLKOUT2_GATE_EN_advancedPage + DYNAMIC_CLKIN_EN_basicPage false - CLKOUT0_REQ_DUTY_basicPage - 50.0000 - 4 + STATIC_PHASE4_advancedPage + 16 STATIC_RATIO0_basicPage 24 - CLK_CAS4_EN_basicPage + STATIC_PHASE0_advancedPage + 16 + + + FBMODE_basicPage false - CLKOUT4_REQ_FREQ_basicPage - 50.0000 - 4 + FEEDBACK_DELAY_ENABLE_advancedPage + false - DYNAMIC_PHASE_EN_advancedPage + DYNAMIC_DUTY1_EN_advancedPage false - DYNAMIC_RATIO4_EN_advancedPage + LOOP_MAPPING_EN_advancedPage false - DYNAMIC_PHASE1_EN_advancedPage + CLKOUT2_GATE_EN_advancedPage false - STATIC_RATIO2_basicPage + DYNAMIC_PHASE2_EN_advancedPage + false + + + STATIC_DUTY2_basicPage 120 - CLK_CAS2_EN_basicPage - false + FBDIV_SEL_advancedPage + 0 - CLKOUT2_REQ_DUTY_basicPage + CLKOUT1_REQ_DUTY_basicPage 50.0000 4 - STATIC_RATIO3_advancedPage - 16 - - - DEVICE_PGL35 + CLKIN_SEL_EN_ENABLE_advancedPage false - STATIC_RATIO4_basicPage + STATIC_DUTY1_advancedPage 16 - FB_MODE_basicPage - 0 + CLKIN_SEL_ENABLE_advancedPage + false - CLKOUT4_GATE_EN_basicPage - false + CLKIN_FREQ_basicPage + 10.0000 + 4 - STATIC_PHASE3_advancedPage - 16 + CLKOUT0_EXT_EN_basicPage + false - STATIC_PHASE4_basicPage + STATIC_DUTY3_basicPage 16 - CLKOUT2_REQ_FREQ_basicPage - 5.0000 - 4 + STATIC_RATIOM_basicPage + 1 - CLKOUT1_REQ_DUTY_basicPage - 50.0000 - 4 + VCODIV2_ENABLE_advancedPage + false - PLL_PWD_ENABLE_basicPage + DYNAMIC_RATIO2_EN_advancedPage false - DYNAMIC_DUTY1_EN_advancedPage + DYNAMIC_PHASE_EN_advancedPage false - CLKOUT3_GATE_EN_basicPage - false + CLKOUT4_REQ_PHASE_basicPage + 0.0000 + 4 - CLKOUT0_EN_advancedPage - true + FEEDBACK_DELAY_ENABLE_basicPage + false - STATIC_DUTY2_advancedPage - 16 + CLKOUT3_REQ_PHASE_basicPage + 0.0000 + 4 - CLKOUT5_EN_advancedPage - false + CLKOUT4_REQ_FREQ_basicPage + 50.0000 + 4 - CLK_CAS3_EN_basicPage - false + BANDWIDTH_basicPage + LOW - DYNAMIC_RATIO3_EN_advancedPage - false + STATIC_DUTY0_advancedPage + 16 - CLKOUT3_GATE_EN_advancedPage - false + STATIC_RATIO2_basicPage + 120 CLKSWITCH_FLAG_ENABLE_basicPage @@ -198,210 +198,192 @@ 16 - DYNAMIC_DUTY0_EN_advancedPage - false - - - STATIC_PHASE1_basicPage + STATIC_DUTY2_advancedPage 16 - CLKOUT5_SEL_advancedPage - 0 - - - CLKOUT0_REQ_PHASE_basicPage - 0.0000 - 4 - - - CLK_CAS3_EN_advancedPage + CLKOUT4_GATE_EN_basicPage false - CLKOUT0_EXT_EN_basicPage + PLL_PWD_ENABLE_basicPage false - CLKOUT4_GATE_EN_advancedPage - false + STATIC_DUTY3_advancedPage + 16 - STATIC_DUTY1_basicPage - 60 + CLKOUT0_EN_advancedPage + true - BANDWIDTH_advancedPage - OPTIMIZED + CLKOUT2_REQ_FREQ_basicPage + 5.0000 + 4 - CLKOUT2_GATE_EN_basicPage + DYNAMIC_CLKIN_EN_advancedPage false - BANDWIDTH_basicPage - OPTIMIZED + CLKOUT1_GATE_EN_advancedPage + false - CLKIN_SEL_ENABLE_advancedPage + CLKOUT0_GATE_EN_advancedPage false - CLKIN_FREQ_basicPage - 50.0000 - 4 + STATIC_PHASE1_advancedPage + 16 - STATIC_RATIOF_basicPage - 24 + CLKOUT2_GATE_EN_basicPage + false - STATIC_DUTY2_basicPage - 120 + DYNAMIC_RATIOF_EN_advancedPage + false - STATIC_RATIOM_advancedPage - 1 + STATIC_RATIOI_advancedPage + 2 - CLKOUT3_EN_basicPage + CLKOUT0_EXT_GATE_EN_advancedPage false - MODE - false + STATIC_DUTY1_basicPage + 60 - FBMODE_basicPage - false + CLKOUT2_EN_basicPage + true - CLKOUT5_GATE_EN_advancedPage - false + CLKOUT2_REQ_DUTY_basicPage + 50.0000 + 4 - CLKIN_SEL_EN_ENABLE_advancedPage + CLKOUT1_GATE_EN_basicPage false - MODE_CFG + FBDIV_SEL_basicPage 0 - FEEDBACK_DELAY_VALUE_basicPage - 0.000 - 3 + STATIC_PHASE0_basicPage + 16 - RST_ENABLE_advancedPage + FBMODE_advancedPage false - DYNAMIC_DUTY3_EN_advancedPage + DYNAMIC_DUTY2_EN_advancedPage false - STATIC_RATIOF_advancedPage - 16 - - - CLKOUT2_EN_basicPage - true + CLKOUT0_REQ_PHASE_basicPage + 0.0000 + 4 - STATIC_DUTY4_basicPage - 16 + CLKOUT0_EXT_GATE_EN_basicPage + false - CLKSWITCH_FLAG_ENABLE_advancedPage + RSTODIV_ENABLE_advancedPage false - FEEDBACK_DELAY_ENABLE_advancedPage + DYNAMIC_PHASE3_EN_advancedPage false - CLKOUT3_REQ_DUTY_basicPage - 50.0000 - 4 + DYNAMIC_RATIO4_EN_advancedPage + false - FBMODE_advancedPage + DYNAMIC_RATIOM_EN_advancedPage false - RST_ENABLE_basicPage + CLKOUT4_EN_basicPage false - FEEDBACK_DELAY_VALUE_advancedPage - 0.000 - 3 + STATIC_RATIOM_advancedPage + 1 - STATIC_DUTY0_basicPage - 24 + MODE_CFG + 0 - STATIC_RATIO0_advancedPage - 16 + CLK_CAS1_EN_advancedPage + false - DYNAMIC_RATIO2_EN_advancedPage - false + STATIC_RATIO4_advancedPage + 16 - CLKOUT1_EN_advancedPage - false + CLKOUT0_EN_basicPage + true - DYNAMIC_DUTY2_EN_advancedPage + DYNAMIC_RATIO1_EN_advancedPage false - VCODIV2_ENABLE_advancedPage + PFDEN_EN_advancedPage false - DYNAMIC_PHASE4_EN_advancedPage - false + CLKOUT1_REQ_FREQ_basicPage + 10.0000 + 4 - STATIC_PHASE0_basicPage + STATIC_DUTY4_basicPage 16 - CLK_CAS1_EN_advancedPage - false + STATIC_DUTY4_advancedPage + 16 - DYNAMIC_PHASE2_EN_advancedPage + DEVICE_PGL35 false - CLKOUT1_REQ_FREQ_basicPage - 10.0000 - 4 + STATIC_RATIO2_advancedPage + 16 - CLKIN_BYPASS_EN_advancedPage - false + STATIC_PHASE1_basicPage + 16 - DYNAMIC_RATIOF_EN_advancedPage - false + CLKIN_FREQ_advancedPage + 50.0000 + 4 - CLKOUT1_REQ_PHASE_basicPage - 0.0000 - 4 + FB_MODE_advancedPage + 0 - CLKOUT4_EN_advancedPage + CLKOUT2_EN_advancedPage false - PFDEN_EN_advancedPage + CLKOUT4_GATE_EN_advancedPage false @@ -409,90 +391,86 @@ 16 - DYNAMIC_CLKIN_EN_advancedPage + CLKOUT5_SEL_advancedPage + 0 + + + CLK_CAS1_EN_basicPage false - CLKOUT2_EN_advancedPage + DYNAMIC_RATIO3_EN_advancedPage false - STATIC_PHASE0_advancedPage + STATIC_PHASE4_basicPage 16 - STATIC_RATIO1_advancedPage + STATIC_RATIO0_advancedPage 16 - RSTODIV_ENABLE_advancedPage + DYNAMIC_LOOP_EN_advancedPage false - STATIC_DUTYF_basicPage - 24 - - - CLKOUT1_GATE_EN_basicPage + MODE false - DYNAMIC_LOOP_EN_advancedPage + SHOW_SETTING_EN_basicPage false - CLKOUT3_EN_advancedPage + CLKOUT3_EN_basicPage false - CLKOUT3_REQ_PHASE_basicPage - 0.0000 - 4 + PLL_PWD_ENABLE_advancedPage + false - LOOP_MAPPING_EN_advancedPage + CLKOUT3_EN_advancedPage false - PLL_PWD_ENABLE_advancedPage + CLKIN_BYPASS_EN_basicPage false - STATIC_DUTY4_advancedPage - 16 + STATIC_RATIOF_basicPage + 60 - CLKOUT1_GATE_EN_advancedPage + CLK_CAS4_EN_advancedPage false + FEEDBACK_DELAY_VALUE_advancedPage + 0.000 + 3 + + CLKOUT4_REQ_DUTY_basicPage 50.0000 4 - STATIC_PHASE2_advancedPage - 16 - - - DYNAMIC_DUTY4_EN_advancedPage + DYNAMIC_PHASE1_EN_advancedPage false - FEEDBACK_DELAY_ENABLE_basicPage - false + STATIC_RATIO4_basicPage + 16 - DYNAMIC_RATIO1_EN_advancedPage + CLK_CAS3_EN_basicPage false - STATIC_RATIOI_advancedPage - 2 - - - CLKOUT0_EN_basicPage - true + STATIC_DUTY0_basicPage + 24 CLKOUT2_REQ_PHASE_basicPage @@ -500,119 +478,141 @@ 4 - STATIC_DUTY1_advancedPage + STATIC_PHASE2_advancedPage 16 - FBDIV_SEL_basicPage - 0 + CLKOUT4_EN_advancedPage + false - STATIC_RATIOM_basicPage - 1 + CLKIN_BYPASS_EN_advancedPage + false - DEVICE_PGL22 - true + STATIC_DUTYF_basicPage + 60 - CLKOUT0_EXT_GATE_EN_advancedPage + CLKOUT3_GATE_EN_advancedPage false - SHOW_SETTING_EN_basicPage - false + FEEDBACK_DELAY_VALUE_basicPage + 0.000 + 3 - CLK_CAS4_EN_advancedPage + CLK_CAS2_EN_advancedPage false - STATIC_RATIOI_basicPage - 2 + STATIC_PHASE3_basicPage + 16 - FB_MODE_advancedPage - 0 + STATIC_RATIO1_basicPage + 60 - CLKIN_SEL_ENABLE_basicPage + CLKOUT3_GATE_EN_basicPage false - CLKOUT0_EXT_GATE_EN_basicPage - false + CLKOUT3_REQ_DUTY_basicPage + 50.0000 + 4 - STATIC_PHASE3_basicPage - 16 + CLKOUT1_REQ_PHASE_basicPage + 0.0000 + 4 - STATIC_RATIO2_advancedPage - 16 + CLKOUT0_REQ_FREQ_basicPage + 25.0000 + 4 - CLKOUT0_GATE_EN_advancedPage + DYNAMIC_DUTY3_EN_advancedPage false - CLKOUT1_EN_basicPage - true + BANDWIDTH_advancedPage + OPTIMIZED - CLKOUT0_REQ_FREQ_basicPage - 25.0000 - 4 + DYNAMIC_RATIO0_EN_advancedPage + false - STATIC_DUTY3_advancedPage + STATIC_RATIO3_advancedPage 16 - CLK_CAS2_EN_advancedPage + CLK_CAS4_EN_basicPage false - FBDIV_SEL_advancedPage - 0 + STATIC_PHASE3_advancedPage + 16 - CLKIN_FREQ_advancedPage - 50.0000 - 4 + CLKOUT5_GATE_EN_advancedPage + false - STATIC_PHASE1_advancedPage - 16 + CLKIN_SEL_ENABLE_basicPage + false - CLK_CAS1_EN_basicPage + DYNAMIC_RATIOI_EN_advancedPage false - STATIC_RATIO4_advancedPage - 16 + CLKOUT1_EN_basicPage + true - DYNAMIC_PHASE3_EN_advancedPage + DYNAMIC_PHASE0_EN_advancedPage false - CLKIN_BYPASS_EN_basicPage + DEVICE_PGL12 false - STATIC_RATIO1_basicPage - 60 + CLKOUT0_GATE_EN_basicPage + false - DEVICE_PGL12 + DYNAMIC_DUTY0_EN_advancedPage false - DYNAMIC_PHASE0_EN_advancedPage + CLK_CAS2_EN_basicPage false + + STATIC_RATIOI_basicPage + 1 + + + DYNAMIC_DUTY4_EN_advancedPage + false + + + CLKIN_SEL_EN_ENABLE_basicPage + false + + + STATIC_RATIOF_advancedPage + 16 + + + STATIC_RATIO1_advancedPage + 16 + diff --git a/ipcore/SPLL/SPLL.v b/ipcore/SPLL/SPLL.v index c71a4d2..43448c9 100644 --- a/ipcore/SPLL/SPLL.v +++ b/ipcore/SPLL/SPLL.v @@ -26,20 +26,20 @@ module SPLL ( pll_lock ); - localparam real CLKIN_FREQ = 50.0; - localparam integer STATIC_RATIOI = 2; + localparam real CLKIN_FREQ = 10.0; + localparam integer STATIC_RATIOI = 1; localparam integer STATIC_RATIO0 = 24; localparam integer STATIC_RATIO1 = 60; localparam integer STATIC_RATIO2 = 120; localparam integer STATIC_RATIO3 = 16; localparam integer STATIC_RATIO4 = 16; - localparam integer STATIC_RATIOF = 24; + localparam integer STATIC_RATIOF = 60; localparam integer STATIC_DUTY0 = 24; localparam integer STATIC_DUTY1 = 60; localparam integer STATIC_DUTY2 = 120; localparam integer STATIC_DUTY3 = 16; localparam integer STATIC_DUTY4 = 16; - localparam integer STATIC_DUTYF = 24; + localparam integer STATIC_DUTYF = 60; localparam integer STATIC_PHASE0 = 16; localparam integer STATIC_PHASE1 = 16; localparam integer STATIC_PHASE2 = 16; @@ -58,7 +58,7 @@ module SPLL ( localparam CLKOUT4_GATE_EN = "FALSE"; localparam FBMODE = "FALSE"; localparam integer FBDIV_SEL = 0; - localparam BANDWIDTH = "OPTIMIZED"; + localparam BANDWIDTH = "LOW"; localparam PFDEN_EN = "FALSE"; localparam VCOCLK_DIV2 = 1'b0; localparam DYNAMIC_RATIOI_EN = "FALSE"; diff --git a/ipcore/SPLL/SPLL_tb.v b/ipcore/SPLL/SPLL_tb.v index 60dd5fe..d6ae836 100644 --- a/ipcore/SPLL/SPLL_tb.v +++ b/ipcore/SPLL/SPLL_tb.v @@ -20,7 +20,7 @@ module SPLL_tb (); -localparam CLKIN_FREQ = 50.0; +localparam CLKIN_FREQ = 10.0; localparam integer FBDIV_SEL = 0; localparam FBMODE = "FALSE"; diff --git a/ipcore/SPLL/generate.log b/ipcore/SPLL/generate.log index b19aeb5..48d2ac2 100644 --- a/ipcore/SPLL/generate.log +++ b/ipcore/SPLL/generate.log @@ -1,6 +1,6 @@ IP Generator (Version 2021.1-SP7 build 86875) Check out license ... -Start generating at 2024-01-07 14:25 +Start generating at 2024-01-10 21:58 Instance: SPLL (D:\workspace\fpga_demo\led_test\ipcore\SPLL\SPLL.idf) IP: PLL (1.5) Part: Logos-PGL22G-MBG324--6 diff --git a/led_test.pds b/led_test.pds index a716644..1e69bb0 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Wed Jan 10 21:54:43 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Wed Jan 10 22:04:09 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-09T21:35:11") + (_timespec "2024-01-10T22:04:02") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -59,7 +59,7 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-01-09T11:35:46") + (_timespec "2024-01-10T22:03:32") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) @@ -138,9 +138,9 @@ (_widget wgt_my_ips_src (_input (_ip "ipcore/SPLL/SPLL.idf" - (_timespec "2024-01-07T14:25:26") + (_timespec "2024-01-10T21:58:34") (_ip_source_item "ipcore/SPLL/SPLL.v" - (_timespec "2024-01-07T14:25:26") + (_timespec "2024-01-10T21:58:33") ) ) (_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf" @@ -195,21 +195,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-10T20:00:19") + (_timespec "2024-01-10T22:04:07") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-10T20:00:18") + (_timespec "2024-01-10T22:04:05") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-10T20:00:19") + (_timespec "2024-01-10T22:04:07") ) ) ) @@ -219,27 +219,13 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 3)) + (_gci_state (_integer 1)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) - (_db_output - (_file "synthesize/Top_syn.adf" - (_format adif) - (_timespec "2024-01-10T20:00:28") - ) - ) (_output - (_file "synthesize/Top_syn.vm" - (_format structural_verilog) - (_timespec "2024-01-10T20:00:29") - ) - (_file "synthesize/Top.snr" - (_format text) - (_timespec "2024-01-10T20:00:29") - ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-10T20:00:29") + (_timespec "2024-01-10T22:04:09") ) ) ) @@ -263,7 +249,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-09T15:13:07") + (_timespec "2024-01-10T21:59:05") ) ) ) diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index c776361..0fe5b0a 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -7,6 +7,7 @@ // module ttl_output #( parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000, parameter TEST = 0, parameter ID = 1 ) ( @@ -131,7 +132,7 @@ module ttl_output #( ); zutils_pwm_generator #( - .SYS_CLOCK_FREQ(50000000), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .OUTPUT_FREQ(1000 * ID) ) _test_signal_generator ( .clk(clk), diff --git a/source/src/top.v b/source/src/top.v index 3fcf862..588547d 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -1,8 +1,8 @@ `include "config.v" `timescale 1ns / 1ns module Top ( - input sys_clk, - input rst_n, + input ex_clk, + input ex_rst_n, /******************************************************************************* * genlock * @@ -108,19 +108,24 @@ module Top ( localparam HARDWARE_TEST_MODE = 1; + + SPLL spll ( - .clkin1(sys_clk), // input + .clkin1(ex_clk), // input .pll_lock(pll_lock), // output .clkout0(sys_clk_25m), // output .clkout1(sys_clk_10m), // output .clkout2(sys_clk_5m) // output ); + assign sys_clk = sys_clk_10m; + assign sys_rst_n = ex_rst_n &pll_lock; + localparam SYS_CLOCK_FREQ = 10000000; - zutils_reset_sig_gen reset_sig_gen_inst ( - .clk(sys_clk), - .rst_n(rst_n), - .rst_n_out(sys_rst_n) - ); +// zutils_reset_sig_gen reset_sig_gen_inst ( +// .clk(sys_clk), +// .rst_n(rst_n), +// .rst_n_out(sys_rst_n) +// ); /******************************************************************************* @@ -238,7 +243,7 @@ module Top ( wire [31:0] ttl_output_module_source_sig_af; zutils_pwm_generator #( - .SYS_CLOCK_FREQ(50000000), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .OUTPUT_FREQ(100) ) pwm100hz_gen ( .clk(sys_clk), @@ -268,6 +273,7 @@ module Top ( ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT1), .TEST(HARDWARE_TEST_MODE), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(1) ) ttl_output_1 ( .clk (sys_clk), @@ -287,6 +293,7 @@ module Top ( ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT2), .TEST(HARDWARE_TEST_MODE), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(2) ) ttl_output_2 ( .clk (sys_clk), @@ -306,6 +313,7 @@ module Top ( ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT3), .TEST(HARDWARE_TEST_MODE), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(3) ) ttl_output_3 ( .clk (sys_clk), @@ -325,6 +333,7 @@ module Top ( ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT4), .TEST(HARDWARE_TEST_MODE), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(4) ) ttl_output_4 ( .clk (sys_clk),