12 changed files with 341 additions and 393 deletions
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BINACPGL22G核心板原理图.pdf
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17README.md
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164led_test.fdc
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104led_test.pds
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196source/src/des_ttl_generator.v
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54source/src/top.v
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25source/src/zutils/zutils_debug_led.v
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48source/src/zutils/zutils_edge_detecter.v
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29source/src/zutils/zutils_multiplexer_4t1.v
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10source/src/zutils/zutils_pluse_generator.v
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44source/src/zutils/zutils_register.v
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43source/test/test_top.v
@ -0,0 +1,17 @@ |
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``` |
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核心板引脚分配: |
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|
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define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} |
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define_attribute {p:rst_n} {PAP_IO_LOC} {U12} |
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define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} |
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define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} |
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|
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define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT} |
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define_attribute {p:sys_clk} {PAP_IO_LOC} {B5} |
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define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3} |
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define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} |
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|
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|
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|
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``` |
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@ -1,145 +1,105 @@ |
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// `include "zutils/zutils_edge_detecter.v" |
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// `include "zutils/zutils_pluse_generator.v" |
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// `include "zutils/zutils_register.v" |
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// |
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// @功能: |
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// 1. 功能:同步输出,脉冲输出 |
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// 2. 输出脉冲 |
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// 3. 输出脉冲时长可调 |
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// 4. 输出极性可调 |
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// |
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module des_ttl_generator #( |
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parameter REG_START_ADD = 0 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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//regbus interface |
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output [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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//寄存器读写接口 |
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output [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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inout wire [31:0] rd_data, |
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|
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inout wire [31:0] rd_data, //received serial data |
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// 输入 |
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input signal_in, |
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//输出 |
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output reg ttloutput //ttl原始数据 |
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input signal_in, //输入信号 |
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output ttloutput //ttl输出信号 |
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); |
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// |
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// @功能: |
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// 1. 功能:同步输出,脉冲输出 |
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// 2. 输出脉冲 |
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// 3. 输出脉冲时长可调 |
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// 4. 输出极性可调 |
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// |
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// |
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// @寄存器列表: |
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// 地址 读写 默认 描述 |
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// 0x00 wr 0x0 模式 0:同步输出 1:脉冲输出 |
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// 0x01 wr 0x0 脉冲模式-脉冲触发方式 0:上升沿 1:下降沿触发 |
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// 0x02 wr 0x0 脉冲模式-有效电平长度: 0~0xffffffff |
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// 0x03 wr 0x0 输出极性 0:正极性 1:极性翻转 |
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// |
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|
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parameter ADD_NUM = 5; //寄存器数量 |
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|
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parameter REG_FUNC_ADD = REG_START_ADD + 0; //功能寄存器地址 |
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parameter REG_PULSE_MODE_ADD = REG_START_ADD + 1; //脉冲模式寄存器地址 |
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parameter REG_PULSE_MODE_RISE_FALL_ADD = REG_START_ADD + 2; //脉冲模式-脉冲触发方式寄存器地址 |
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parameter REG_PULSE_MODE_VALID_LEN_ADD = REG_START_ADD + 3; //脉冲模式-有效电平长度寄存器地址 |
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parameter REG_OUTPUT_POLARITY_ADD = REG_START_ADD + 4; //输出极性寄存器地址 |
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|
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reg ttl_origin_output; //ttl原始信号输出 |
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wire ttl_after_process_output; //ttl处理后信号输出 |
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|
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assign signal_in_a = signal_in; //信号输入 |
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reg signal_in_b = 0; //信号输入延迟一周期 |
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|
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|
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/******************************************************************************* |
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* 寄存器读写 * |
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* 寄存器列表 * |
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*******************************************************************************/ |
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// parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 |
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// reg [31:0] register[REG_START_ADD:REG_END_ADD]; |
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// integer i; |
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// always @(posedge clk or negedge rst_n) begin |
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// if (!rst_n) begin |
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// for (i = 0; i < ADD_NUM; i = i + 1) begin |
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// register[i] <= 0; |
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// end |
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// end else begin |
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// if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; |
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// end |
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// end |
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// assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; |
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|
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// |
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// 模式寄存器 |
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// [0] 0:同步输出 1:脉冲输出 |
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wire [31:0] reg_function; |
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|
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// |
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// 配置寄存器 |
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// [0] 脉冲输入时候触发信号 0:上升沿 1:下降沿触发 |
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// [1] 输出极性控制位 0:输出高电平 1:输出低电平 |
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// |
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wire [31:0] reg_config; |
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assign pluse_input_trigger_signal = reg_config[0]; |
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assign output_polarity = !reg_config[1]; |
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|
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zutils_register #( |
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.REG_START_ADD(REG_START_ADD), |
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.ADD_NUM(5) |
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// |
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// 脉冲模式-有效电平长度: |
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// 0~0xffffffff |
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// |
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wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff |
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//脉冲输出 |
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wire pluse_output; |
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// 输入信号上升沿事件 |
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wire in_signal_rising_edge; |
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// 输入信号下降沿事件 |
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wire in_signal_falling_edge; |
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// 输入信号上升沿或下降沿事件 |
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wire in_signal_edge; |
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// 输出的脉冲触发信号的触发信号 |
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wire signal_src_trigger; |
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|
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assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge); |
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|
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zutils_register16 #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.addr(addr), |
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.wr_data(wr_data), |
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.wr_en(wr_en), |
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.rd_data(rd_data) |
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.rd_data(rd_data), |
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.reg0(reg_function), |
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.reg1(reg_config), |
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.reg2(reg_pulse_mode_valid_len) |
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); |
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|
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// zutils_edge_detecter _signal_in ( |
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// .clk(clk), |
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// .rst_n(rst_n), |
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// .signal_in(signal_in) |
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// ); |
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zutils_edge_detecter _signal_in ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(signal_in), |
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.in_signal_rising_edge(in_signal_rising_edge), |
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.in_signal_falling_edge(in_signal_falling_edge), |
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.in_signal_edge(in_signal_edge) |
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); |
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|
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zutils_pluse_generator _pluse_generator ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.pluse_width(reg_pulse_mode_valid_len), |
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.trigger(signal_src_trigger), |
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.output_signal(ttl_after_process_output) |
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); |
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|
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|
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/******************************************************************************* |
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* signal_a and signal_b * |
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*******************************************************************************/ |
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// signal_in 脉冲信号捕获 |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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signal_in_b <= 0; |
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end else begin |
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signal_in_b <= signal_in_a; |
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end |
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end |
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/******************************************************************************* |
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* 脉冲模式输出 * |
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*******************************************************************************/ |
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// 电平计数 |
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reg [31:0] signal_output_duration_cnt; |
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assign signal_src_trigger = (_register.data[REG_PULSE_MODE_RISE_FALL_ADD] == 0) ? (signal_in_a & ~signal_in_b) : (~signal_in_a & signal_in_b); |
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// 通过计数输出波形 |
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assign ttl_after_process_output = (signal_output_duration_cnt < _register.data[REG_PULSE_MODE_VALID_LEN_ADD]) ? 1 : 0; |
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// 脉冲计数 |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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signal_output_duration_cnt <= 0; |
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end else begin |
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// 脉冲模式 |
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if (_register.data[REG_FUNC_ADD] == 1) begin |
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if (signal_src_trigger == 1) begin |
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signal_output_duration_cnt <= 0; |
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end else begin |
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signal_output_duration_cnt <= signal_output_duration_cnt + 1; |
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end |
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end // 非脉冲模式 |
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else begin |
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signal_output_duration_cnt <= 0; |
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end |
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end |
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end |
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/******************************************************************************* |
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* 信号输出控制 * |
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*******************************************************************************/ |
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reg ttloutput; |
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always @(*) begin |
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case (_register.data[REG_FUNC_ADD]) |
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0: begin |
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ttloutput = (_register.data[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_origin_output : !ttl_origin_output; |
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end |
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1: begin |
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ttloutput = (_register.data[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_after_process_output : !ttl_after_process_output; |
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end |
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default: ttloutput = 0; |
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endcase |
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end |
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assign output_signal0 = (output_polarity == 1) ? signal_in : !signal_in; |
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assign output_signal1 = (output_polarity == 1) ? ttl_after_process_output : !ttl_after_process_output; |
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|
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zutils_multiplexer_4t1 multiplexer_4t1 ( |
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.chooseindex(reg_function), |
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.signal0(output_signal0), |
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.signal1(output_signal1), |
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.signal2(0), |
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.signal3(0), |
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.signalout(ttloutput) |
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); |
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|
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endmodule |
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@ -0,0 +1,25 @@ |
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module zutils_debug_led #( |
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parameter PERIOD_COUNT = 1000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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output reg debug_led |
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); |
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|
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reg [31:0] counter; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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counter <= 0; |
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debug_led <= 1'b0; |
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end else begin |
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if (counter == PERIOD_COUNT - 1) begin |
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counter <= 0; |
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debug_led <= ~debug_led; |
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end else begin |
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counter <= counter + 1; |
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end |
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end |
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end |
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|
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endmodule |
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@ -1,44 +1,44 @@ |
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module zutils_edge_detecter ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input wire signal_in |
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|
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input wire in_signal, |
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output reg in_signal_last, |
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output reg in_signal_rising_edge, |
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output reg in_signal_falling_edge, |
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output reg in_signal_edge |
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); |
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|
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reg signal_in_last = 0; |
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assign now = signal_in; |
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assign last = signal_in_last; |
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|
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reg rsing_edge_signal; |
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reg falling_edge_signal; |
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reg edge_sginal; |
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// reg in_signal_rising_edge; |
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// reg in_signal_falling_edge; |
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// reg in_signal_edge; |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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signal_in_last <= 0; |
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in_signal_last <= 0; |
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end else begin |
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signal_in_last <= signal_in; |
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in_signal_last <= in_signal; |
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end |
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end |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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rsing_edge_signal <= 0; |
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falling_edge_signal <= 0; |
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edge_sginal <= 0; |
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in_signal_rising_edge <= 0; |
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in_signal_falling_edge <= 0; |
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in_signal_edge <= 0; |
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end else begin |
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if (signal_in_last == 0 && signal_in == 1) begin |
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rsing_edge_signal <= 1; |
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falling_edge_signal <= 0; |
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edge_sginal <= 1; |
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end else if (signal_in_last == 1 && signal_in == 0) begin |
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rsing_edge_signal <= 0; |
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falling_edge_signal <= 1; |
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edge_sginal <= 1; |
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if (in_signal_last == 0 && in_signal == 1) begin |
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in_signal_rising_edge <= 1; |
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in_signal_falling_edge <= 0; |
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in_signal_edge <= 1; |
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end else if (in_signal_last == 1 && in_signal == 0) begin |
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in_signal_rising_edge <= 0; |
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in_signal_falling_edge <= 1; |
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in_signal_edge <= 1; |
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end else begin |
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rsing_edge_signal <= 0; |
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falling_edge_signal <= 0; |
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edge_sginal <= 0; |
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in_signal_rising_edge <= 0; |
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in_signal_falling_edge <= 0; |
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in_signal_edge <= 0; |
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end |
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end |
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end |
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|
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@ -0,0 +1,29 @@ |
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module zutils_multiplexer_4t1 ( |
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input [31:0] chooseindex, |
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input wire signal0, |
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input wire signal1, |
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input wire signal2, |
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input wire signal3, |
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output reg signalout |
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); |
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|
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always @(*) begin |
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case (chooseindex) |
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0: begin |
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signalout = signal0; |
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end |
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1: begin |
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signalout = signal1; |
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end |
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2: begin |
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signalout = signal2; |
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end |
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3: begin |
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signalout = signal3; |
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end |
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default: begin |
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signalout = 0; |
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end |
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endcase |
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end |
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endmodule |
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