diff --git a/ACPGL22G核心板原理图.pdf b/ACPGL22G核心板原理图.pdf new file mode 100644 index 0000000..e80a7db Binary files /dev/null and b/ACPGL22G核心板原理图.pdf differ diff --git a/README.md b/README.md new file mode 100644 index 0000000..60531db --- /dev/null +++ b/README.md @@ -0,0 +1,17 @@ +``` +核心板引脚分配: + +define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:rst_n} {PAP_IO_LOC} {U12} +define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} +define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} + +define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:sys_clk} {PAP_IO_LOC} {B5} +define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} + + + + +``` \ No newline at end of file diff --git a/led_test.fdc b/led_test.fdc index eaebcfc..acac9ec 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -1,53 +1,3 @@ -#define_attribute {p:led[3]} {PAP_IO_DIRECTION} {OUTPUT} -#define_attribute {p:led[3]} {PAP_IO_LOC} {U12} -#define_attribute {p:led[3]} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:led[3]} {PAP_IO_STANDARD} {LVCMOS33} -#define_attribute {p:led[3]} {PAP_IO_DRIVE} {4} -#define_attribute {p:led[3]} {PAP_IO_SLEW} {SLOW} -#define_attribute {p:led[2]} {PAP_IO_DIRECTION} {OUTPUT} -#define_attribute {p:led[2]} {PAP_IO_LOC} {B5} -#define_attribute {p:led[2]} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:led[2]} {PAP_IO_STANDARD} {LVCMOS33} -#define_attribute {p:led[2]} {PAP_IO_DRIVE} {4} -#define_attribute {p:led[2]} {PAP_IO_SLEW} {SLOW} -#define_attribute {p:led[1]} {PAP_IO_DIRECTION} {OUTPUT} -#define_attribute {p:led[1]} {PAP_IO_LOC} {U10} -#define_attribute {p:led[1]} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:led[1]} {PAP_IO_STANDARD} {LVCMOS33} -#define_attribute {p:led[1]} {PAP_IO_DRIVE} {4} -#define_attribute {p:led[1]} {PAP_IO_SLEW} {SLOW} -#define_attribute {p:led[0]} {PAP_IO_DIRECTION} {OUTPUT} -#define_attribute {p:led[0]} {PAP_IO_LOC} {R11} -#define_attribute {p:led[0]} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:led[0]} {PAP_IO_STANDARD} {LVCMOS33} -#define_attribute {p:led[0]} {PAP_IO_DRIVE} {4} -#define_attribute {p:led[0]} {PAP_IO_SLEW} {SLOW} -#define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} -#define_attribute {p:rst_n} {PAP_IO_LOC} {U11} -#define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} -#define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT} -#define_attribute {p:sys_clk} {PAP_IO_LOC} {V11} -#define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:led[3]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:led[3]} {PAP_IO_LOC} {V11} -define_attribute {p:led[3]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:led[3]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:led[3]} {PAP_IO_DRIVE} {4} -define_attribute {p:led[3]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:led[2]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:led[2]} {PAP_IO_LOC} {U11} -define_attribute {p:led[2]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:led[2]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:led[2]} {PAP_IO_DRIVE} {4} -define_attribute {p:led[2]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:led[1]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:led[1]} {PAP_IO_LOC} {V10} -define_attribute {p:led[1]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:led[1]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:led[1]} {PAP_IO_DRIVE} {4} -define_attribute {p:led[1]} {PAP_IO_SLEW} {SLOW} define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:rst_n} {PAP_IO_LOC} {U12} define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} @@ -56,111 +6,9 @@ define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:sys_clk} {PAP_IO_LOC} {B5} define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3} define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} -#create_clock -name {} -period {10.000} -waveform {0.000 5.000} -#define_attribute {p:sys_clk} {PAP_IO_HYS_DRIVE_MODE} {NOHYS} -#define_attribute {p:uart_tx} {PAP_IO_DIRECTION} {OUTPUT} -#define_attribute {p:uart_tx} {PAP_IO_LOC} {T11} -#define_attribute {p:uart_tx} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:uart_tx} {PAP_IO_STANDARD} {LVCMOS33} -#define_attribute {p:uart_tx} {PAP_IO_DRIVE} {4} -#define_attribute {p:uart_tx} {PAP_IO_SLEW} {SLOW} -#define_attribute {p:tx_TxD_start} {PAP_IO_DIRECTION} {OUTPUT} -#define_attribute {p:tx_TxD_start} {PAP_IO_LOC} {T11} -#define_attribute {p:tx_TxD_start} {PAP_IO_VCCIO} {3.3} -#define_attribute {p:tx_TxD_start} {PAP_IO_STANDARD} {LVCMOS33} -#define_attribute {p:tx_TxD_start} {PAP_IO_DRIVE} {4} -#define_attribute {p:tx_TxD_start} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[3]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[3]} {PAP_IO_LOC} {T11} -define_attribute {p:test_io[3]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[3]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[3]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[3]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[4]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[4]} {PAP_IO_LOC} {R11} -define_attribute {p:test_io[4]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[4]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[4]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[4]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[5]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[5]} {PAP_IO_LOC} {P12} -define_attribute {p:test_io[5]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[5]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[5]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[5]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[6]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[6]} {PAP_IO_LOC} {P11} -define_attribute {p:test_io[6]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[6]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[6]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[6]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[7]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[7]} {PAP_IO_LOC} {T13} -define_attribute {p:test_io[7]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[7]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[7]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[7]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[8]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[8]} {PAP_IO_LOC} {R13} -define_attribute {p:test_io[8]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[8]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[8]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[8]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[9]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[9]} {PAP_IO_LOC} {P13} -define_attribute {p:test_io[9]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[9]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[9]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[9]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[10]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[10]} {PAP_IO_LOC} {P14} -define_attribute {p:test_io[10]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[10]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[10]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[10]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[11]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[11]} {PAP_IO_LOC} {R15} -define_attribute {p:test_io[11]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[11]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[11]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[11]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[12]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[12]} {PAP_IO_LOC} {R14} -define_attribute {p:test_io[12]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[12]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[12]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[12]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[13]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[13]} {PAP_IO_LOC} {T16} -define_attribute {p:test_io[13]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[13]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[13]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[13]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[14]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[14]} {PAP_IO_LOC} {R16} -define_attribute {p:test_io[14]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[14]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[14]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[14]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[15]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[15]} {PAP_IO_LOC} {U16} -define_attribute {p:test_io[15]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[15]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[15]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[15]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:test_io[16]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:test_io[16]} {PAP_IO_LOC} {V16} -define_attribute {p:test_io[16]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:test_io[16]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:test_io[16]} {PAP_IO_DRIVE} {4} -define_attribute {p:test_io[16]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:usb_serial_tx} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:usb_serial_tx} {PAP_IO_LOC} {C10} -define_attribute {p:usb_serial_tx} {PAP_IO_VCCIO} {3.3} -define_attribute {p:usb_serial_tx} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:usb_serial_tx} {PAP_IO_DRIVE} {4} -define_attribute {p:usb_serial_tx} {PAP_IO_SLEW} {SLOW} -define_attribute {p:usb_serial_rx} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:usb_serial_rx} {PAP_IO_LOC} {A12} -define_attribute {p:usb_serial_rx} {PAP_IO_VCCIO} {3.3} -define_attribute {p:usb_serial_rx} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {E2} +define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} +define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} diff --git a/led_test.pds b/led_test.pds index 6834ce7..7e69221 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Dec 31 15:14:14 2023") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Jan 6 19:37:09 2024") (_version "1.0.5") (_status "initial") (_project @@ -27,7 +27,7 @@ ) (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2023-12-31T15:13:50") + (_timespec "2024-01-06T19:24:54") ) (_file "source/src/uart_tx.v" (_format verilog) @@ -59,19 +59,27 @@ ) (_file "source/src/des_ttl_generator.v" (_format verilog) - (_timespec "2023-12-31T15:12:53") + (_timespec "2023-12-31T17:25:29") ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) - (_timespec "2023-12-31T14:50:20") + (_timespec "2023-12-31T16:28:46") ) (_file "source/src/zutils/zutils_edge_detecter.v" (_format verilog) - (_timespec "2023-12-31T15:00:01") + (_timespec "2023-12-31T16:39:25") ) (_file "source/src/zutils/zutils_register.v" (_format verilog) - (_timespec "2023-12-31T14:53:25") + (_timespec "2023-12-31T16:33:39") + ) + (_file "source/src/zutils/zutils_multiplexer_4t1.v" + (_format verilog) + (_timespec "2023-12-31T17:16:29") + ) + (_file "source/src/zutils/zutils_debug_led.v" + (_format verilog) + (_timespec "2024-01-06T19:12:28") ) ) ) @@ -92,7 +100,7 @@ (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2023-12-14T21:55:40") + (_timespec "2024-01-06T19:22:21") ) ) ) @@ -114,15 +122,15 @@ (_format verilog) (_timespec "2023-12-13T19:30:23") ) - (_file "source/test/test_top.v" + (_file "source/test/test_top.v" + "test_top:" (_format verilog) - (_timespec "2023-12-13T21:56:53") + (_timespec "2024-01-06T19:37:07") ) (_file "source/test/test_uart_reg_reader.v" (_format verilog) (_timespec "2023-12-15T22:18:26") ) - (_file "source/test/test_spi_reg_reader.v" + "test_spi_reg_reader:" + (_file "source/test/test_spi_reg_reader.v" (_format verilog) (_timespec "2023-12-15T22:10:16") ) @@ -135,17 +143,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2023-12-31T15:14:05") + (_timespec "2024-01-06T19:25:01") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2023-12-31T15:14:04") + (_timespec "2024-01-06T19:25:01") ) (_file "compile/cmr.db" (_format text) - (_timespec "2023-12-31T15:14:05") + (_timespec "2024-01-06T19:25:01") ) ) ) @@ -161,21 +169,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2023-12-31T15:14:07") + (_timespec "2024-01-06T19:25:03") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2023-12-31T15:14:07") + (_timespec "2024-01-06T19:25:03") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2023-12-31T15:14:07") + (_timespec "2024-01-06T19:25:03") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2023-12-31T15:14:07") + (_timespec "2024-01-06T19:25:03") ) ) ) @@ -196,21 +204,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2023-12-31T15:14:09") + (_timespec "2024-01-06T19:25:06") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2023-12-31T15:14:09") + (_timespec "2024-01-06T19:25:06") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2023-12-31T15:14:09") + (_timespec "2024-01-06T19:25:06") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2023-12-31T15:14:09") + (_timespec "2024-01-06T19:25:06") ) ) ) @@ -219,7 +227,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2023-12-31T15:14:09") + (_timespec "2024-01-06T19:25:06") ) ) ) @@ -233,33 +241,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2023-12-31T15:14:13") + (_timespec "2024-01-06T19:25:12") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2023-12-31T15:14:13") + (_timespec "2024-01-06T19:25:12") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2023-12-31T15:14:13") + (_timespec "2024-01-06T19:25:12") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2023-12-31T15:14:12") + (_timespec "2024-01-06T19:25:12") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2023-12-31T15:14:12") + (_timespec "2024-01-06T19:25:11") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2023-12-31T15:14:13") + (_timespec "2024-01-06T19:25:12") ) (_file "place_route/prr.db" (_format text) - (_timespec "2023-12-31T15:14:14") + (_timespec "2024-01-06T19:25:12") ) ) ) @@ -270,8 +278,24 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_attribute _auto_exe_lock (_switch OFF)) + (_db_output + (_file "report_timing/Top_rtp.adf" + (_format adif) + (_timespec "2024-01-06T19:25:15") + ) + ) + (_output + (_file "report_timing/Top.rtr" + (_format text) + (_timespec "2024-01-06T19:25:15") + ) + (_file "report_timing/rtr.db" + (_format text) + (_timespec "2024-01-06T19:25:15") + ) + ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -289,7 +313,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-01-06T19:25:19") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-01-06T19:25:19") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-01-06T19:25:19") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-01-06T19:25:19") + ) + ) ) ) ) diff --git a/source/src/des_ttl_generator.v b/source/src/des_ttl_generator.v index 01d5dcc..456fd22 100644 --- a/source/src/des_ttl_generator.v +++ b/source/src/des_ttl_generator.v @@ -1,145 +1,105 @@ -// `include "zutils/zutils_edge_detecter.v" -// `include "zutils/zutils_pluse_generator.v" -// `include "zutils/zutils_register.v" +// +// @功能: +// 1. 功能:同步输出,脉冲输出 +// 2. 输出脉冲 +// 3. 输出脉冲时长可调 +// 4. 输出极性可调 +// module des_ttl_generator #( parameter REG_START_ADD = 0 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active - //regbus interface - output [31:0] addr, - input [31:0] wr_data, - input wr_en, + //寄存器读写接口 + output [31:0] addr, + input [31:0] wr_data, + input wr_en, + inout wire [31:0] rd_data, - inout wire [31:0] rd_data, //received serial data - // 输入 - input signal_in, - //输出 - output reg ttloutput //ttl原始数据 + input signal_in, //输入信号 + output ttloutput //ttl输出信号 ); - // - // @功能: - // 1. 功能:同步输出,脉冲输出 - // 2. 输出脉冲 - // 3. 输出脉冲时长可调 - // 4. 输出极性可调 - // - // - // @寄存器列表: - // 地址 读写 默认 描述 - // 0x00 wr 0x0 模式 0:同步输出 1:脉冲输出 - // 0x01 wr 0x0 脉冲模式-脉冲触发方式 0:上升沿 1:下降沿触发 - // 0x02 wr 0x0 脉冲模式-有效电平长度: 0~0xffffffff - // 0x03 wr 0x0 输出极性 0:正极性 1:极性翻转 - // - - parameter ADD_NUM = 5; //寄存器数量 - - parameter REG_FUNC_ADD = REG_START_ADD + 0; //功能寄存器地址 - parameter REG_PULSE_MODE_ADD = REG_START_ADD + 1; //脉冲模式寄存器地址 - parameter REG_PULSE_MODE_RISE_FALL_ADD = REG_START_ADD + 2; //脉冲模式-脉冲触发方式寄存器地址 - parameter REG_PULSE_MODE_VALID_LEN_ADD = REG_START_ADD + 3; //脉冲模式-有效电平长度寄存器地址 - parameter REG_OUTPUT_POLARITY_ADD = REG_START_ADD + 4; //输出极性寄存器地址 - - reg ttl_origin_output; //ttl原始信号输出 - wire ttl_after_process_output; //ttl处理后信号输出 - - assign signal_in_a = signal_in; //信号输入 - reg signal_in_b = 0; //信号输入延迟一周期 - /******************************************************************************* - * 寄存器读写 * + * 寄存器列表 * *******************************************************************************/ - // parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 - // reg [31:0] register[REG_START_ADD:REG_END_ADD]; - // integer i; - // always @(posedge clk or negedge rst_n) begin - // if (!rst_n) begin - // for (i = 0; i < ADD_NUM; i = i + 1) begin - // register[i] <= 0; - // end - // end else begin - // if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; - // end - // end - // assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; - + // + // 模式寄存器 + // [0] 0:同步输出 1:脉冲输出 + wire [31:0] reg_function; + // + // 配置寄存器 + // [0] 脉冲输入时候触发信号 0:上升沿 1:下降沿触发 + // [1] 输出极性控制位 0:输出高电平 1:输出低电平 + // + wire [31:0] reg_config; + assign pluse_input_trigger_signal = reg_config[0]; + assign output_polarity = !reg_config[1]; - zutils_register #( - .REG_START_ADD(REG_START_ADD), - .ADD_NUM(5) + // + // 脉冲模式-有效电平长度: + // 0~0xffffffff + // + wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff + + //脉冲输出 + wire pluse_output; + // 输入信号上升沿事件 + wire in_signal_rising_edge; + // 输入信号下降沿事件 + wire in_signal_falling_edge; + // 输入信号上升沿或下降沿事件 + wire in_signal_edge; + // 输出的脉冲触发信号的触发信号 + wire signal_src_trigger; + + assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge); + + zutils_register16 #( + .REG_START_ADD(REG_START_ADD) ) _register ( .clk(clk), .rst_n(rst_n), .addr(addr), .wr_data(wr_data), .wr_en(wr_en), - .rd_data(rd_data) + .rd_data(rd_data), + .reg0(reg_function), + .reg1(reg_config), + .reg2(reg_pulse_mode_valid_len) ); - // zutils_edge_detecter _signal_in ( - // .clk(clk), - // .rst_n(rst_n), - // .signal_in(signal_in) - // ); + zutils_edge_detecter _signal_in ( + .clk(clk), + .rst_n(rst_n), + .in_signal(signal_in), + .in_signal_rising_edge(in_signal_rising_edge), + .in_signal_falling_edge(in_signal_falling_edge), + .in_signal_edge(in_signal_edge) + ); + zutils_pluse_generator _pluse_generator ( + .clk(clk), + .rst_n(rst_n), + .pluse_width(reg_pulse_mode_valid_len), + .trigger(signal_src_trigger), + .output_signal(ttl_after_process_output) + ); - /******************************************************************************* - * signal_a and signal_b * - *******************************************************************************/ - // signal_in 脉冲信号捕获 - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - signal_in_b <= 0; - end else begin - signal_in_b <= signal_in_a; - end - end - /******************************************************************************* - * 脉冲模式输出 * - *******************************************************************************/ - // 电平计数 - reg [31:0] signal_output_duration_cnt; - assign signal_src_trigger = (_register.data[REG_PULSE_MODE_RISE_FALL_ADD] == 0) ? (signal_in_a & ~signal_in_b) : (~signal_in_a & signal_in_b); - // 通过计数输出波形 - assign ttl_after_process_output = (signal_output_duration_cnt < _register.data[REG_PULSE_MODE_VALID_LEN_ADD]) ? 1 : 0; - // 脉冲计数 - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - signal_output_duration_cnt <= 0; - end else begin - // 脉冲模式 - if (_register.data[REG_FUNC_ADD] == 1) begin - if (signal_src_trigger == 1) begin - signal_output_duration_cnt <= 0; - end else begin - signal_output_duration_cnt <= signal_output_duration_cnt + 1; - end - end // 非脉冲模式 - else begin - signal_output_duration_cnt <= 0; - end - end - end - /******************************************************************************* - * 信号输出控制 * - *******************************************************************************/ - reg ttloutput; - always @(*) begin - case (_register.data[REG_FUNC_ADD]) - 0: begin - ttloutput = (_register.data[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_origin_output : !ttl_origin_output; - end - 1: begin - ttloutput = (_register.data[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_after_process_output : !ttl_after_process_output; - end - default: ttloutput = 0; - endcase - end + assign output_signal0 = (output_polarity == 1) ? signal_in : !signal_in; + assign output_signal1 = (output_polarity == 1) ? ttl_after_process_output : !ttl_after_process_output; + + zutils_multiplexer_4t1 multiplexer_4t1 ( + .chooseindex(reg_function), + .signal0(output_signal0), + .signal1(output_signal1), + .signal2(0), + .signal3(0), + .signalout(ttloutput) + ); endmodule diff --git a/source/src/top.v b/source/src/top.v index bc52724..363006c 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -2,28 +2,40 @@ module Top ( input sys_clk, input rst_n, - output reg [3:0] led, - output reg [3:0] key, - output wire usb_serial_tx, - input wire usb_serial_rx, - output wire [35:3] test_io -); - wire inclkpll_clk0out; - inclkpll inclkpll_inst ( - .clkin1 (sys_clk), - .clkout0(inclkpll_clk0out) - ); - -des_ttl_generator des_ttl_generator_inst ( - .clk(sys_clk), - .rst_n(rst_n), - .addr(), - .wr_data(0), - .wr_en(0), - .rd_data(), - .signal_in(1), - .ttloutput(test_io[3]) + + output wire core_board_debug_led ); + zutils_debug_led #( + .PERIOD_COUNT(10000000) + ) core_board_debug_led_inst ( + .clk(sys_clk), + .rst_n(rst_n), + .debug_led(core_board_debug_led) + ); + + +// +// +// +// + +// wire inclkpll_clk0out; +// inclkpll inclkpll_inst ( +// .clkin1 (sys_clk), +// .clkout0(inclkpll_clk0out) +// ); + +// des_ttl_generator des_ttl_generator_inst ( +// .clk(sys_clk), +// .rst_n(rst_n), +// .addr(), +// .wr_data(0), +// .wr_en(0), +// .rd_data(), +// .signal_in(1), +// .ttloutput(test_io[3]) +// ); + endmodule diff --git a/source/src/zutils/zutils_debug_led.v b/source/src/zutils/zutils_debug_led.v new file mode 100644 index 0000000..0d7eecd --- /dev/null +++ b/source/src/zutils/zutils_debug_led.v @@ -0,0 +1,25 @@ +module zutils_debug_led #( + parameter PERIOD_COUNT = 1000000 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + output reg debug_led +); + + reg [31:0] counter; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + counter <= 0; + debug_led <= 1'b0; + end else begin + if (counter == PERIOD_COUNT - 1) begin + counter <= 0; + debug_led <= ~debug_led; + end else begin + counter <= counter + 1; + end + end + end + +endmodule diff --git a/source/src/zutils/zutils_edge_detecter.v b/source/src/zutils/zutils_edge_detecter.v index eb63e72..fb26fa9 100644 --- a/source/src/zutils/zutils_edge_detecter.v +++ b/source/src/zutils/zutils_edge_detecter.v @@ -1,44 +1,44 @@ module zutils_edge_detecter ( input clk, //clock input input rst_n, //asynchronous reset input, low active - input wire signal_in - + input wire in_signal, + output reg in_signal_last, + output reg in_signal_rising_edge, + output reg in_signal_falling_edge, + output reg in_signal_edge ); - reg signal_in_last = 0; - assign now = signal_in; - assign last = signal_in_last; - reg rsing_edge_signal; - reg falling_edge_signal; - reg edge_sginal; + // reg in_signal_rising_edge; + // reg in_signal_falling_edge; + // reg in_signal_edge; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - signal_in_last <= 0; + in_signal_last <= 0; end else begin - signal_in_last <= signal_in; + in_signal_last <= in_signal; end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - rsing_edge_signal <= 0; - falling_edge_signal <= 0; - edge_sginal <= 0; + in_signal_rising_edge <= 0; + in_signal_falling_edge <= 0; + in_signal_edge <= 0; end else begin - if (signal_in_last == 0 && signal_in == 1) begin - rsing_edge_signal <= 1; - falling_edge_signal <= 0; - edge_sginal <= 1; - end else if (signal_in_last == 1 && signal_in == 0) begin - rsing_edge_signal <= 0; - falling_edge_signal <= 1; - edge_sginal <= 1; + if (in_signal_last == 0 && in_signal == 1) begin + in_signal_rising_edge <= 1; + in_signal_falling_edge <= 0; + in_signal_edge <= 1; + end else if (in_signal_last == 1 && in_signal == 0) begin + in_signal_rising_edge <= 0; + in_signal_falling_edge <= 1; + in_signal_edge <= 1; end else begin - rsing_edge_signal <= 0; - falling_edge_signal <= 0; - edge_sginal <= 0; + in_signal_rising_edge <= 0; + in_signal_falling_edge <= 0; + in_signal_edge <= 0; end end end diff --git a/source/src/zutils/zutils_multiplexer_4t1.v b/source/src/zutils/zutils_multiplexer_4t1.v new file mode 100644 index 0000000..2b784bb --- /dev/null +++ b/source/src/zutils/zutils_multiplexer_4t1.v @@ -0,0 +1,29 @@ +module zutils_multiplexer_4t1 ( + input [31:0] chooseindex, + input wire signal0, + input wire signal1, + input wire signal2, + input wire signal3, + output reg signalout +); + + always @(*) begin + case (chooseindex) + 0: begin + signalout = signal0; + end + 1: begin + signalout = signal1; + end + 2: begin + signalout = signal2; + end + 3: begin + signalout = signal3; + end + default: begin + signalout = 0; + end + endcase + end +endmodule diff --git a/source/src/zutils/zutils_pluse_generator.v b/source/src/zutils/zutils_pluse_generator.v index c7a37d3..6d15866 100644 --- a/source/src/zutils/zutils_pluse_generator.v +++ b/source/src/zutils/zutils_pluse_generator.v @@ -4,7 +4,9 @@ module zutils_pluse_generator ( input wire [31:0] pluse_width, input wire trigger, - output reg pluse + output reg output_signal + + ); reg [31:0] counter = 0; @@ -12,14 +14,14 @@ module zutils_pluse_generator ( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin counter <= 0; - pluse <= 0; + output_signal <= 0; end else begin if (trigger) begin counter <= pluse_width; - pluse <= 1; + output_signal <= 1; end else begin if (counter == 0) begin - pluse <= 0; + output_signal <= 0; end else begin counter <= counter - 1; end diff --git a/source/src/zutils/zutils_register.v b/source/src/zutils/zutils_register.v index 2406014..c73a467 100644 --- a/source/src/zutils/zutils_register.v +++ b/source/src/zutils/zutils_register.v @@ -1,6 +1,5 @@ -module zutils_register #( - parameter REG_START_ADD = 0, - parameter ADD_NUM = 10 +module zutils_register16 #( + parameter REG_START_ADD = 0 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active @@ -10,11 +9,48 @@ module zutils_register #( input [31:0] wr_data, input wr_en, - inout wire [31:0] rd_data //received serial data + inout wire [31:0] rd_data, //received serial data + + output [31:0] reg0, + output [31:0] reg1, + output [31:0] reg2, + output [31:0] reg3, + output [31:0] reg4, + output [31:0] reg5, + output [31:0] reg6, + output [31:0] reg7, + output [31:0] reg8, + output [31:0] reg9, + output [31:0] regA, + output [31:0] regB, + output [31:0] regC, + output [31:0] regD, + output [31:0] regE, + output [31:0] regF ); + localparam ADD_NUM = 16; //寄存器数量 parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 reg [31:0] data[REG_START_ADD:REG_END_ADD]; + + + assign reg0 = data[0]; + assign reg1 = data[1]; + assign reg2 = data[2]; + assign reg3 = data[3]; + assign reg4 = data[4]; + assign reg5 = data[5]; + assign reg6 = data[6]; + assign reg7 = data[7]; + assign reg8 = data[8]; + assign reg9 = data[9]; + assign regA = data[10]; + assign regB = data[11]; + assign regC = data[12]; + assign regD = data[13]; + assign regE = data[14]; + assign regF = data[15]; + integer i; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin diff --git a/source/test/test_top.v b/source/test/test_top.v index 28845a0..69cd527 100644 --- a/source/test/test_top.v +++ b/source/test/test_top.v @@ -1,41 +1,18 @@ -`timescale 1ns / 1ns +`timescale 10ns / 10ns module test_top; - // Inputs - reg clk_50m; - reg rst_n; + reg sys_clk; + reg rst_n; - wire rxclk_en; - wire txclk_en; - - wire [3:0] led; - wire test_io3; - wire test_io4; - wire test_io5; - wire test_io6; - wire test_io7; - wire test_io8; - wire test_io9; - wire test_io10; - wire test_io11; + wire core_board_debug_led; Top top_impl ( - .sys_clk(clk_50m), + .sys_clk(sys_clk), .rst_n(rst_n), - .led(led), - .test_io3(test_io3), - .test_io4(test_io4), - .test_io5(test_io5), - .test_io6(test_io6), - .test_io7(test_io7), - .test_io8(test_io8), - .test_io9(test_io9), - .test_io10(test_io10), - .test_io11(test_io11) + .core_board_debug_led(core_board_debug_led) ); initial begin - // Initialize Inputs - clk_50m = 0; + sys_clk = 0; rst_n = 0; #100; @@ -43,8 +20,8 @@ module test_top; #15; - #300000; - $stop; + // #5000000; + // $stop; end - always #10 clk_50m = ~clk_50m; //20ns 50MHZ + always #1 sys_clk = ~sys_clk; // 50MHZ时钟 endmodule