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fpga_led_test
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zhaohe 2 years ago
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9 changed files with 79 additions and 162 deletions
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  1. 128
      led_test.pds
  2. 7
      msg_level.txt
  3. 7
      source/src/timecode/timecode_generator.v
  4. 8
      source/src/timecode/timecode_serialization.v
  5. 22
      source/src/top.v
  6. 13
      source/src/xsync_internal_generator.v
  7. 2
      source/src/zutils/zutils_register.v
  8. 2
      source/src/zutils/zutils_register_advanced.v
  9. 26
      source/test/test_top.v

128
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Jan 11 12:54:38 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Jan 11 16:07:12 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-01-11T11:16:40")
(_timespec "2024-01-11T15:58:27")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -35,7 +35,7 @@
)
(_file "source/src/zutils/zutils_register.v"
(_format verilog)
(_timespec "2024-01-09T20:18:53")
(_timespec "2024-01-11T15:21:44")
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
@ -87,7 +87,7 @@
)
(_file "source/src/xsync_internal_generator.v"
(_format verilog)
(_timespec "2024-01-11T12:54:37")
(_timespec "2024-01-11T16:04:31")
)
(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
(_format verilog)
@ -95,7 +95,7 @@
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
(_timespec "2024-01-09T20:00:43")
(_timespec "2024-01-11T15:21:48")
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
@ -127,11 +127,11 @@
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-01-10T21:45:29")
(_timespec "2024-01-11T16:07:11")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-01-10T21:12:26")
(_timespec "2024-01-11T15:07:28")
)
)
)
@ -174,9 +174,9 @@
(_format verilog)
(_timespec "2023-12-13T19:30:23")
)
(_file "source/test/test_top.v"
(_file "source/test/test_top.v" + "test_top:"
(_format verilog)
(_timespec "2024-01-10T21:14:18")
(_timespec "2024-01-11T16:00:43")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
@ -186,7 +186,7 @@
(_format verilog)
(_timespec "2023-12-15T22:10:16")
)
(_file "source/test/test_timecode_generator.v" + "test_timecode_generator:"
(_file "source/test/test_timecode_generator.v"
(_format verilog)
(_timespec "2024-01-10T21:54:42")
)
@ -199,17 +199,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-01-11T11:46:53")
(_timespec "2024-01-11T15:27:50")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-01-11T11:46:51")
(_timespec "2024-01-11T15:27:48")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-01-11T11:46:53")
(_timespec "2024-01-11T15:27:50")
)
)
)
@ -225,21 +225,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-01-11T11:47:22")
(_timespec "2024-01-11T15:28:05")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-01-11T11:47:25")
(_timespec "2024-01-11T15:28:06")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-01-11T11:47:27")
(_timespec "2024-01-11T15:28:07")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-01-11T11:47:28")
(_timespec "2024-01-11T15:28:07")
)
)
)
@ -256,27 +256,7 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 3))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-01-11T11:47:31")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-01-11T11:47:30")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-01-11T11:47:31")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-01-11T11:47:31")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
@ -293,39 +273,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 3))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-01-11T11:49:15")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-01-11T11:49:15")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-01-11T11:49:14")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-01-11T11:49:14")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-01-11T11:48:24")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-01-11T11:49:15")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-01-11T11:49:16")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -334,24 +282,8 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 3))
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-01-11T11:49:21")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-01-11T11:49:21")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-01-11T11:49:22")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -369,25 +301,7 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 3))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-01-11T11:49:40")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-01-11T11:49:40")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-01-11T11:49:40")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-01-11T11:49:42")
)
)
(_gci_state (_integer 0))
)
)
)

7
msg_level.txt
View File

@ -0,0 +1,7 @@
Verilog-2019=3
Verilog-2020=0
Verilog-2021=0
Verilog-2023=0
Verilog-2024=0
Verilog-2036=0
Verilog-2042=0

7
source/src/timecode/timecode_generator.v
View File

@ -60,7 +60,9 @@ module timecode_generator #(
if (!rst_n) begin
timecode <= 0;
timecode_trigger_sig <= 0;
end else if (!en) begin
end else begin
if (!en) begin
if (timecode0_wen || timecode1_wen) begin
if (timecode0_wen) begin
timecode[31:0] <= timecode0;
@ -79,6 +81,9 @@ module timecode_generator #(
timecode_trigger_sig <= 0;
end
end
end
end
assign timecode0_export = timecode[31:0];

8
source/src/timecode/timecode_serialization.v
View File

@ -132,7 +132,7 @@ module timecode_serialization #(
// bit trigger sig gen
reg [31:0] halfbitcount;
reg bit_tigger_sig;
always @(posedge clk) begin
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
halfbitcount <= 0;
bit_tigger_sig <= 0;
@ -163,7 +163,7 @@ module timecode_serialization #(
// 偏移
reg [ 1:0] onebitoff;
reg [31:0] bitoff;
always @(posedge clk) begin
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
onebitoff <= 0;
bitoff <= 0;
@ -195,7 +195,7 @@ module timecode_serialization #(
end
// 时码输出
always @(posedge clk) begin
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out_timecode_serial_data <= 0;
end else begin
@ -241,7 +241,7 @@ module timecode_serialization #(
// out_trigger_sig
// out_timecode
always @(posedge clk) begin
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out_trigger_sig <= 0;
out_timecode <= 0;

22
source/src/top.v
View File

@ -109,7 +109,7 @@ module Top (
localparam REG_ADD_OFF_STM32 = 16'h0000;
localparam REG_ADD_OFF_FPGA_TEST = 16'h00020;
//控制中心寄存器地址
localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030;
localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030; // 48
//输入组件
localparam REG_ADD_OFF_TTLIN1 = 16'h0100;
localparam REG_ADD_OFF_TTLIN2 = 16'h0110;
@ -283,26 +283,6 @@ module Top (
assign ttl_output_module_source_sig_af[31] = ISIG_internal_100hz ;
wire ISIG_logic0; // 逻辑0
wire ISIG_logic1; // 逻辑1
wire ISIG_ttlin1_module_ext; // ttl1输入模块原始信号
wire ISIG_ttlin1_module_divide; // ttl1输入模块分频信号
wire ISIG_ttlin2_module_ext; // ttl2输入模块原始信号
wire ISIG_ttlin2_module_divide; // ttl2输入模块分频信号
wire ISIG_ttlin3_module_ext; // ttl3输入模块原始信号
wire ISIG_ttlin3_module_divide; // ttl3输入模块分频信号
wire ISIG_ttlin4_module_ext; // ttl4输入模块原始信号
wire ISIG_ttlin4_module_divide; // ttl4输入模块分频信号
wire ISIG_en_flag_internal; // 内部使能状态信号输出
wire ISIG_genlock_frame_sync_ext; // 外部genlock帧同步信号
wire ISIG_genlock_frame_sync_internal; // 内部genlock帧同步信号
wire ISIG_timecode_frame_sync_ext; // 外部timecode帧同步信号
wire ISIG_timecode_frame_sync_internal; // 内部timecode帧同步信号
wire ISIG_timecode_serial_data_ext; // 外部timecode串行数据输入
wire ISIG_timecode_serial_data_internal; // 内部timecode串行数据输入
wire ISIG_internal_100hz; // 100hz测试信号
xsync_internal_generator #(
.REG_START_ADD (REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR),

13
source/src/xsync_internal_generator.v
View File

@ -192,8 +192,10 @@ module xsync_internal_generator #(
if (reg_wr_sig && reg_wr_index == CTRL_REG_INDEX) begin
if (wr_data[0] == 1) begin
rC_work_state[0] <= 1;
rC_work_state[31:1] <= 0;
end else begin
rC_work_state[0] <= 0;
rC_work_state[31:1] <= 0;
end
end
@ -206,9 +208,12 @@ module xsync_internal_generator #(
//外部电平控制
if (ext_ttlinx_module_raw_sig == 1) begin
rC_work_state[0] <= 1;
rC_work_state[31:1] <= 0;
end else begin
rC_work_state[0] <= 0;
rC_work_state[31:1] <= 0;
end
end
default: begin
end
@ -240,7 +245,7 @@ module xsync_internal_generator #(
);
zutils_multiplexer_32t1_v2 genlock_clk_output_mult (
.chooseindex(genlock_format),
.chooseindex(r2_genlock_format),
//in
.in0(genlock_fps2397_clk),
.in1(genlock_fps2398_clk),
@ -259,6 +264,8 @@ module xsync_internal_generator #(
/*******************************************************************************
* smpte_timecode_clk_generator *
*******************************************************************************/
assign timecode0_wen = reg_wr_sig && reg_wr_index == 6;
assign timecode1_wen = reg_wr_sig && reg_wr_index == 7;
timecode_generator #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@ -268,9 +275,9 @@ module xsync_internal_generator #(
.timecode_format(r3_timecode_format),
.timecode0_wen(addr == 6),
.timecode0_wen(timecode0_wen),
.timecode0(wr_data),
.timecode1_wen(addr == 7),
.timecode1_wen(timecode1_wen),
.timecode1(wr_data),
.timecode0_export(r6_timecode0),

2
source/src/zutils/zutils_register.v
View File

@ -46,7 +46,7 @@ module zutils_register16 #(
output [31:0] regF
);
parameter REG_END_ADD = REG_START_ADD + 16 - 1; //寄存器结束地址
localparam REG_END_ADD = REG_START_ADD + 16 - 1; //寄存器结束地址
reg [31:0] data[0:15];
assign reg0 = data[0];

2
source/src/zutils/zutils_register_advanced.v
View File

@ -32,7 +32,7 @@ module zutils_register_advanced #(
output reg [31:0] reg_index
);
parameter REG_END_ADD = REG_START_ADD + 16 - 1; //寄存器结束地址
localparam REG_END_ADD = REG_START_ADD + 16 - 1; //寄存器结束地址
// always @(posedge clk or negedge rst_n) begin
// if (!rst_n) begin

26
source/test/test_top.v
View File

@ -1,4 +1,4 @@
`timescale 5ns / 5ns
`timescale 10ns / 10ns
module test_top;
reg sys_clk;
reg rst_n;
@ -36,31 +36,32 @@ module test_top;
begin
addr[15] = 1;
spi2_cs_pin = 0;
#30; // 100ns
#3000; // 100ns
for (i = 0; i < 48; i = i + 1) begin
spi2_clk_pin = 0;
if (i <= 15) spi2_tx_pin = addr[i];
else spi2_tx_pin = data[i-16];
#30;
#300;
spi2_clk_pin = 1;
#30;
#300;
end
spi2_clk_pin = 0;
#10;
#300;
spi2_clk_pin = 1;
#20;
#200;
spi2_cs_pin = 1;
spi2_tx_pin = 1;
#300;
#3000;
end
endtask
Top top_impl (
.sys_clk(sys_clk),
.rst_n(rst_n),
.ex_clk(sys_clk),
.ex_rst_n(rst_n),
.core_board_debug_led(core_board_debug_led),
.spi2_cs_pin (spi2_cs_pin),
@ -87,7 +88,7 @@ module test_top;
rst_n = 1;
#100;
#1000;
spi_write_reg(16'h0020, 32'h00000001);
spi_write_reg(16'h0021, 32'h00000010);
spi_write_reg(16'h0022, 32'h00000100);
@ -98,8 +99,11 @@ module test_top;
spi_write_reg(16'h0022, 32'h00000200);
spi_write_reg(16'h0023, 32'h00002000);
spi_write_reg(16'h00030+6, 32'h12345678); // 写SignalGenerator——TIMECODE0
spi_write_reg(16'h00030+7, 32'h87654321); // 写SignalGenerator——TIMECODE0
#100000000;
$stop;
end
always #1 sys_clk = ~sys_clk; // 50MHZ时钟
always #5 sys_clk = ~sys_clk; // 50MHZ时钟
endmodule
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