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@ -34,19 +34,7 @@ |
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// GENLOCK_FPS5994_FORMAT = 7 |
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// GENLOCK_FPS6000_FORMAT = 8 |
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// |
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// 触发方式 |
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// 0.寄存器触发 |
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// 1.外部TTL输入1_高电平触发 |
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// 2.外部TTL输入1_低电平触发 |
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// 3.外部TTL输入2_高电平触发 |
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// 4.外部TTL输入2_低电平触发 |
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// 5.外部TTL输入3_高电平触发 |
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// 6.外部TTL输入3_低电平触发 |
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// 7.外部TTL输入4_高电平触发 |
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// 8.外部TTL输入4_低电平触发 |
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// 9.外部TIMECODE触发 |
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// |
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module xsync_internal_generator #( |
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parameter REG_START_ADD = 0, |
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@ -86,36 +74,28 @@ module xsync_internal_generator #( |
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/******************************************************************************* |
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* 内部工作状态信号输出 * |
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*******************************************************************************/ |
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output wire out_working_flag |
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output wire out_en_flag |
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); |
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localparam FPS2398Format = 0; |
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localparam FPS2400Format = 1; |
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localparam FPS2500Format = 2; |
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localparam FPS2997Format = 3; |
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localparam FPS2997DropFormat = 4; |
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localparam FPS3000Format = 5; |
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localparam CTRL_REG_INDEX = 4; |
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reg [31:0] r0_start_control_mode_reg; //控制模式选择寄存器 |
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// reg [31:0] r1_stop_control_mode_reg; //控制模式选择寄存器 |
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reg [31:0] r2_genlock_format; //genlock格式寄存器 |
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reg [31:0] r3_timecode_format; //timecode格式寄存器 |
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reg [31:0] r4_control_trigger_reg; // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2] |
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// reg [31:0] r5_control_stop_reg; // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2] |
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reg [31:0] r0_start_control_mode_reg; //控制模式选择寄存器 |
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reg [31:0] r2_genlock_format; //genlock格式寄存器 |
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reg [31:0] r3_timecode_format; //timecode格式寄存器 |
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reg [31:0] r4_control_trigger_reg; // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2] |
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wire [31:0] r6_timecode0; //timecode0 belong to timecode_generator_ist |
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wire [31:0] r7_timecode1; //timecode1 belong to timecode_generator_ist |
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reg [31:0] r8_timecode_start0; // 时码启动寄存器0 |
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reg [31:0] r9_timecode_start1; // 时码启动寄存器1 |
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reg [31:0] rA_timecode_stop0; // 时码停止寄存器0 |
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reg [31:0] rB_timecode_stop1; // 时码停止寄存器1 |
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reg [31:0] rC_work_state; //工作状态 read only |
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assign out_en_flag = rC_work_state[0]; |
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wire [31:0] r6_timecode0; //timecode |
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wire [31:0] r7_timecode1; //Timecode用户位寄存器 |
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reg [31:0] r8_timecode_start_time_code; //Timecode用户位寄存器 H(8bit) M(8bit) S(8bit) F(8bit) |
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reg [31:0] r9_timecode_stop_time_code; //Timecode用户位寄存器 H(8bit) M(8bit) S(8bit) F(8bit) |
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reg [31:0] rA_work_state; //工作状态 |
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//写寄存器标志位 |
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wire [31:0] reg_wr_index; |
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assign out_working_flag = rA_work_state[0]; |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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@ -128,16 +108,16 @@ module xsync_internal_generator #( |
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.rd_data(rd_data), |
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.reg0(r0_start_control_mode_reg), |
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// .reg1(r1_stop_control_mode_reg), |
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.reg2(r2_genlock_format), |
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.reg3(r3_timecode_format), |
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.reg4(r4_control_trigger_reg), |
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// .reg5(r5_control_stop_reg), |
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.reg6(r6_timecode0), |
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.reg7(r7_timecode1), |
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.reg8(r8_timecode_start_time_code), |
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.reg9(r9_timecode_stop_time_code), |
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.regA(rA_work_state), |
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.reg8(r8_timecode_start0), |
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.reg9(r9_timecode_start1), |
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.regA(rA_timecode_stop0), |
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.regB(rB_timecode_stop1), |
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.regC(rC_work_state), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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@ -146,24 +126,28 @@ module xsync_internal_generator #( |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r0_start_control_mode_reg <= 0; |
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// r1_stop_control_mode_reg <= 0; |
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r2_genlock_format <= 0; |
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r3_timecode_format <= 0; |
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r4_control_trigger_reg <= 0; |
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// r5_control_stop_reg <= 0; |
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r8_timecode_start_time_code <= 0; |
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r9_timecode_stop_time_code <= 0; |
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r8_timecode_start0 <= 0; |
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r9_timecode_start1 <= 0; |
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rA_timecode_stop0 <= 0; |
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rB_timecode_stop1 <= 0; |
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// rC_work_state <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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0: r0_start_control_mode_reg <= wr_data; |
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// 1: r1_stop_control_mode_reg <= wr_data; |
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2: r2_genlock_format <= wr_data; |
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3: r3_timecode_format <= wr_data; |
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4: r4_control_trigger_reg <= wr_data; |
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// 5: r5_control_stop_reg <= wr_data; |
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8: r8_timecode_start_time_code <= wr_data; |
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9: r9_timecode_stop_time_code <= wr_data; |
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31'h0: r0_start_control_mode_reg <= wr_data; |
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31'h2: r2_genlock_format <= wr_data; |
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31'h3: r3_timecode_format <= wr_data; |
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31'h4: r4_control_trigger_reg <= wr_data; |
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31'h8: r8_timecode_start0 <= wr_data; |
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31'h9: r9_timecode_start1 <= wr_data; |
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31'hA: rA_timecode_stop0 <= wr_data; |
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31'hB: rB_timecode_stop1 <= wr_data; |
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// 31'hC: rC_work_state <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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@ -176,13 +160,15 @@ module xsync_internal_generator #( |
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// 2.外部触发启动 |
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// 3.TIMECODE触发启动 |
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// 0.寄存器触发 |
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// 1.外部TIMECODE触发 |
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// 2.外部TTL输入1_高电平触发 |
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// 3.外部TTL输入2_高电平触发 |
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// 4.外部TTL输入3_高电平触发 |
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// 5.外部TTL输入4_高电平触发 |
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// 0.寄存器触发,启动停止 |
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// 1.外部TIMECODE触发启动,寄存器控制停止 |
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// 2.外部TTL输入1_高电平触发,低电平停止 |
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// 3.外部TTL输入2_高电平触发,低电平停止 |
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// 4.外部TTL输入3_高电平触发,低电平停止 |
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// 5.外部TTL输入4_高电平触发,低电平停止 |
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// |
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zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi ( |
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.chooseindex(r0_start_control_mode_reg), |
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//in |
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@ -198,17 +184,32 @@ module xsync_internal_generator #( |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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start_sig <= 0; |
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rC_work_state <= 0; |
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end else begin |
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case (r0_start_control_mode_reg[31:0]) |
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0: begin |
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//寄存器控制启动 |
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if (reg_wr_sig && reg_wr_index == CTRL_REG_INDEX) begin |
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if (wr_data[0] == 1) begin |
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rC_work_state[0] <= 1; |
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end else begin |
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rC_work_state[0] <= 0; |
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end |
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end |
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end |
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1: begin |
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//TIMECODE触发 |
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end |
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2, 3, 4, 5: begin |
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//外部电平控制 |
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if (ext_ttlinx_module_raw_sig == 1) begin |
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rC_work_state[0] <= 1; |
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end else begin |
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rC_work_state[0] <= 0; |
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end |
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end |
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default: begin |
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end |
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@ -227,7 +228,7 @@ module xsync_internal_generator #( |
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) genlock ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.ctrl_sig(out_working_flag), |
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.ctrl_sig(out_en_flag), |
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.genlock_fps2397_clk(genlock_fps2397_clk), |
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.genlock_fps2398_clk(genlock_fps2398_clk), |
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.genlock_fps2400_clk(genlock_fps2400_clk), |
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@ -259,37 +260,6 @@ module xsync_internal_generator #( |
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/******************************************************************************* |
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* smpte_timecode_clk_generator * |
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*******************************************************************************/ |
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// |
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// TimeCode 基础控制信号生成 |
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// 1 |
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// |
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// |
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// module timecode_generator #( |
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// parameter SYS_CLOCK_FREQ = 10000000 |
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// ) ( |
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// input clk, //clock input |
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// input rst_n, //asynchronous reset input, low active |
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// input [31:0] timecode_format, |
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// input timecode0_wen, |
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// input [31:0] timecode0, |
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// input timecode1_wen, |
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// input [31:0] timecode1, |
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// input en, |
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// output wire out_timecode_serial_data, |
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// output wire out_trigger_sig, |
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// output wire [31:0] out_timecode0, |
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// output wire [31:0] out_timecode1 |
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// ); |
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// r6_timecode0 |
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// r7_timecode1 |
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timecode_generator #( |
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) |
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@ -307,7 +277,7 @@ module xsync_internal_generator #( |
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.timecode0_export(r6_timecode0), |
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.timecode1_export(r7_timecode1), |
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.en(en), |
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.en(out_en_flag), |
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.out_timecode_serial_data(out_timecode_serial_sig), |
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.out_trigger_sig(out_timecode_tirgger_sig), |
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@ -315,26 +285,5 @@ module xsync_internal_generator #( |
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.out_timecode1(out_timecode_sig[63:32]) |
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); |
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// internal_timecode_generator #( |
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// .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) |
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// ) internal_timecode_generator ( |
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// .clk(clk), |
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// .rst_n(rst_n), |
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// .ctrl_sig(out_working_flag), |
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// .timecode_format(r3_timecode_format), |
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// //寄存器读写接口 |
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// .timecode_tc_wr_data(wr_data), |
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// .timecode_tc_wr_en (reg_wr_index == 6), |
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// .out_timecode_tc_reg(r6_timecode0), |
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// .timecode_uc_wr_data(wr_data), |
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// .timecode_uc_wr_en (reg_wr_index == 7), |
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// .out_timecode_uc_reg(r7_timecode1), |
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// .out_timecode_tirgger_sig(out_timecode_tirgger_sig) |
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// ); |
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// assign out_timecode_sig = {r6_timecode0, r7_timecode1}; |
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endmodule |