diff --git a/led_test.fdc b/led_test.fdc index fb646cc..2a4b1d6 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -76,14 +76,14 @@ # timecode_bnc_in INPUT R15 # timecode_bnc_in_state_led INPUT D18 -# define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:rst_n} {PAP_IO_LOC} {G13} -# define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:sys_clk} {PAP_IO_LOC} {B5} -define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} +# define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT} +# define_attribute {p:ex_rst_n} {PAP_IO_LOC} {G13} +# define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:ex_clk} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:ex_clk} {PAP_IO_LOC} {B5} +define_attribute {p:ex_clk} {PAP_IO_VCCIO} {3.3} +define_attribute {p:ex_clk} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {E2} define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} @@ -569,7 +569,7 @@ define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_VCCIO} {3.3} define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_DRIVE} {4} define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_SLEW} {SLOW} -define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:rst_n} {PAP_IO_LOC} {M16} -define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} -define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:ex_rst_n} {PAP_IO_LOC} {M16} +define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3} +define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33} diff --git a/led_test.pds b/led_test.pds index 1e69bb0..4193bc4 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Wed Jan 10 22:04:09 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Jan 11 09:23:14 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-10T22:04:02") + (_timespec "2024-01-11T09:22:07") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -59,7 +59,7 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-01-10T22:03:32") + (_timespec "2024-01-10T22:09:45") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) @@ -87,7 +87,7 @@ ) (_file "source/src/xsync_internal_generator.v" (_format verilog) - (_timespec "2024-01-10T20:51:41") + (_timespec "2024-01-11T09:21:24") ) (_file "source/src/zutils/zutils_pwm_generator_advanced.v" (_format verilog) @@ -152,7 +152,7 @@ (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2024-01-08T21:48:05") + (_timespec "2024-01-10T22:05:26") ) ) ) @@ -199,17 +199,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-10T22:04:07") + (_timespec "2024-01-11T09:22:17") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-10T22:04:05") + (_timespec "2024-01-11T09:22:16") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-10T22:04:07") + (_timespec "2024-01-11T09:22:17") ) ) ) @@ -219,13 +219,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 1)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) + (_db_output + (_file "synthesize/Top_syn.adf" + (_format adif) + (_timespec "2024-01-11T09:22:26") + ) + ) (_output + (_file "synthesize/Top_syn.vm" + (_format structural_verilog) + (_timespec "2024-01-11T09:22:27") + ) + (_file "synthesize/Top.snr" + (_format text) + (_timespec "2024-01-11T09:22:27") + ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-10T22:04:09") + (_timespec "2024-01-11T09:22:27") ) ) ) @@ -242,14 +256,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2024-01-11T09:22:30") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2024-01-11T09:22:30") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2024-01-11T09:22:30") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2024-01-11T09:22:30") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-10T21:59:05") + (_timespec "2024-01-11T09:22:30") ) ) ) @@ -259,7 +293,39 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-01-11T09:23:00") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-01-11T09:23:00") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-01-11T09:23:00") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-01-11T09:23:00") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-01-11T09:22:49") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-01-11T09:23:00") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-01-11T09:23:00") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -268,8 +334,24 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_attribute _auto_exe_lock (_switch OFF)) + (_db_output + (_file "report_timing/Top_rtp.adf" + (_format adif) + (_timespec "2024-01-11T09:23:05") + ) + ) + (_output + (_file "report_timing/Top.rtr" + (_format text) + (_timespec "2024-01-11T09:23:05") + ) + (_file "report_timing/rtr.db" + (_format text) + (_timespec "2024-01-11T09:23:05") + ) + ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -287,7 +369,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-01-11T09:23:14") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-01-11T09:23:14") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-01-11T09:23:14") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-01-11T09:23:14") + ) + ) ) ) ) diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index 0fe5b0a..8e50f68 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -8,7 +8,7 @@ module ttl_output #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000, - parameter TEST = 0, + // parameter TEST = 0, parameter ID = 1 ) ( input clk, //clock input @@ -48,7 +48,7 @@ module ttl_output #( // 4:原始信号翻转输出 // 5:脉冲输出 // 6:脉冲信号翻转输出 - localparam REG1_INIT = TEST ? 2 : 0; + localparam REG1_INIT = 0; wire [31:0] reg_output_signal_select; // diff --git a/source/src/top.v b/source/src/top.v index 588547d..137b18b 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -117,15 +117,15 @@ module Top ( .clkout1(sys_clk_10m), // output .clkout2(sys_clk_5m) // output ); - assign sys_clk = sys_clk_10m; - assign sys_rst_n = ex_rst_n &pll_lock; + assign sys_clk = sys_clk_10m; + assign sys_rst_n = ex_rst_n & pll_lock; localparam SYS_CLOCK_FREQ = 10000000; -// zutils_reset_sig_gen reset_sig_gen_inst ( -// .clk(sys_clk), -// .rst_n(rst_n), -// .rst_n_out(sys_rst_n) -// ); + // zutils_reset_sig_gen reset_sig_gen_inst ( + // .clk(sys_clk), + // .rst_n(rst_n), + // .rst_n_out(sys_rst_n) + // ); /******************************************************************************* @@ -181,7 +181,6 @@ module Top ( wire [31:0] debuger_rd_data; - /******************************************************************************* * TEST_SPI_REG * *******************************************************************************/ @@ -212,34 +211,31 @@ module Top ( .rd_data(fpga_test_rd_data) ); - xsync_internal_generator xsync_internal_generator_ins ( - .clk (sys_clk), - .rst_n(sys_rst_n) - ); - - /******************************************************************************* - * 输出组件 * + * 信号源 * *******************************************************************************/ - - // level0 = 0, // 0 // level1 = 1, // 1 - wire ttlin1_module_raw_sig; // ttl1输入模块原始信号 2 - wire ttlin1_module_sig_divide; // ttl1输入模块分频信号 3 - wire ttlin2_module_raw_sig; // ttl2输入模块原始信号 4 - wire ttlin2_module_sig_divide; // ttl2输入模块分频信号 5 - wire ttlin3_module_raw_sig; // ttl3输入模块原始信号 6 - wire ttlin3_module_sig_divide; // ttl3输入模块分频信号 7 - wire ttlin4_module_raw_sig; // ttl4输入模块原始信号 8 - wire ttlin4_module_sig_divide; // ttl4输入模块分频信号 9 - wire genlockin_module_freq_sig; // genlock输入模块频率信号 10 - wire timecodein_module_trigger_sig; // timecode输入模块触发信号 11 - wire internal_camera_sync_sig; // 内部相机同步信号 12 - wire internal_timecode_trigger_sig; // 内部timecode触发信号 13 - wire internal_genlock_freq_sig; // 内部genlock频率信号 14 - wire internal_work_state_sig; // 内部工作状态信号 15 - wire internal_100hz_output; // 内部工作状态信号 16 + wire ttlin1_module_raw_sig; // ttl1输入模块原始信号 2 + wire ttlin1_module_sig_divide; // ttl1输入模块分频信号 3 + wire ttlin2_module_raw_sig; // ttl2输入模块原始信号 4 + wire ttlin2_module_sig_divide; // ttl2输入模块分频信号 5 + wire ttlin3_module_raw_sig; // ttl3输入模块原始信号 6 + wire ttlin3_module_sig_divide; // ttl3输入模块分频信号 7 + wire ttlin4_module_raw_sig; // ttl4输入模块原始信号 8 + wire ttlin4_module_sig_divide; // ttl4输入模块分频信号 9 + wire genlockin_module_freq_sig; // genlock输入模块频率信号 10 + wire timecodein_module_trigger_sig; // timecode输入模块触发信号 11 + wire internal_camera_sync_sig; // 内部相机同步信号 12 + wire internal_timecode_trigger_sig; // 内部timecode触发信号 13 + wire internal_genlock_freq_sig; // 内部genlock频率信号 14 + wire internal_work_state_sig; // 内部工作状态信号 15 + wire internal_100hz_output; // 内部工作状态信号 16 + + xsync_internal_generator xsync_internal_generator_ins ( + .clk (sys_clk), + .rst_n(sys_rst_n) + ); wire [31:0] ttl_output_module_source_sig_af; zutils_pwm_generator #( @@ -248,8 +244,18 @@ module Top ( ) pwm100hz_gen ( .clk(sys_clk), .rst_n(sys_rst_n), - .output_signal(pwm100hz) + .output_signal(internal_100hz_output) ); + + + + /******************************************************************************* + * 输出组件 * + *******************************************************************************/ + + + + assign ttl_output_module_source_sig_af[0] = 0; assign ttl_output_module_source_sig_af[1] = 1; assign ttl_output_module_source_sig_af[2] = ttlin1_module_raw_sig; @@ -269,10 +275,8 @@ module Top ( assign ttl_output_module_source_sig_af[16] = internal_100hz_output; - ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT1), - .TEST(HARDWARE_TEST_MODE), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(1) ) ttl_output_1 ( @@ -292,7 +296,6 @@ module Top ( ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT2), - .TEST(HARDWARE_TEST_MODE), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(2) ) ttl_output_2 ( @@ -312,7 +315,6 @@ module Top ( ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT3), - .TEST(HARDWARE_TEST_MODE), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(3) ) ttl_output_3 ( @@ -332,7 +334,6 @@ module Top ( ttl_output #( .REG_START_ADD(`REG_ADD_OFF_TTLOUT4), - .TEST(HARDWARE_TEST_MODE), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), .ID(4) ) ttl_output_4 ( diff --git a/source/src/xsync_internal_generator.v b/source/src/xsync_internal_generator.v index 4e6a3e2..02231a2 100644 --- a/source/src/xsync_internal_generator.v +++ b/source/src/xsync_internal_generator.v @@ -34,19 +34,7 @@ // GENLOCK_FPS5994_FORMAT = 7 // GENLOCK_FPS6000_FORMAT = 8 -// -// 触发方式 -// 0.寄存器触发 -// 1.外部TTL输入1_高电平触发 -// 2.外部TTL输入1_低电平触发 -// 3.外部TTL输入2_高电平触发 -// 4.外部TTL输入2_低电平触发 -// 5.外部TTL输入3_高电平触发 -// 6.外部TTL输入3_低电平触发 -// 7.外部TTL输入4_高电平触发 -// 8.外部TTL输入4_低电平触发 -// 9.外部TIMECODE触发 -// + module xsync_internal_generator #( parameter REG_START_ADD = 0, @@ -86,36 +74,28 @@ module xsync_internal_generator #( /******************************************************************************* * 内部工作状态信号输出 * *******************************************************************************/ - output wire out_working_flag + output wire out_en_flag ); - localparam FPS2398Format = 0; - localparam FPS2400Format = 1; - localparam FPS2500Format = 2; - localparam FPS2997Format = 3; - localparam FPS2997DropFormat = 4; - localparam FPS3000Format = 5; - + localparam CTRL_REG_INDEX = 4; - reg [31:0] r0_start_control_mode_reg; //控制模式选择寄存器 - // reg [31:0] r1_stop_control_mode_reg; //控制模式选择寄存器 - reg [31:0] r2_genlock_format; //genlock格式寄存器 - reg [31:0] r3_timecode_format; //timecode格式寄存器 - reg [31:0] r4_control_trigger_reg; // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2] - // reg [31:0] r5_control_stop_reg; // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2] + reg [31:0] r0_start_control_mode_reg; //控制模式选择寄存器 + reg [31:0] r2_genlock_format; //genlock格式寄存器 + reg [31:0] r3_timecode_format; //timecode格式寄存器 + reg [31:0] r4_control_trigger_reg; // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2] + wire [31:0] r6_timecode0; //timecode0 belong to timecode_generator_ist + wire [31:0] r7_timecode1; //timecode1 belong to timecode_generator_ist + reg [31:0] r8_timecode_start0; // 时码启动寄存器0 + reg [31:0] r9_timecode_start1; // 时码启动寄存器1 + reg [31:0] rA_timecode_stop0; // 时码停止寄存器0 + reg [31:0] rB_timecode_stop1; // 时码停止寄存器1 + reg [31:0] rC_work_state; //工作状态 read only + assign out_en_flag = rC_work_state[0]; - wire [31:0] r6_timecode0; //timecode - wire [31:0] r7_timecode1; //Timecode用户位寄存器 - - reg [31:0] r8_timecode_start_time_code; //Timecode用户位寄存器 H(8bit) M(8bit) S(8bit) F(8bit) - reg [31:0] r9_timecode_stop_time_code; //Timecode用户位寄存器 H(8bit) M(8bit) S(8bit) F(8bit) - - reg [31:0] rA_work_state; //工作状态 + //写寄存器标志位 wire [31:0] reg_wr_index; - assign out_working_flag = rA_work_state[0]; - zutils_register_advanced #( .REG_START_ADD(REG_START_ADD) @@ -128,16 +108,16 @@ module xsync_internal_generator #( .rd_data(rd_data), .reg0(r0_start_control_mode_reg), - // .reg1(r1_stop_control_mode_reg), .reg2(r2_genlock_format), .reg3(r3_timecode_format), .reg4(r4_control_trigger_reg), - // .reg5(r5_control_stop_reg), .reg6(r6_timecode0), .reg7(r7_timecode1), - .reg8(r8_timecode_start_time_code), - .reg9(r9_timecode_stop_time_code), - .regA(rA_work_state), + .reg8(r8_timecode_start0), + .reg9(r9_timecode_start1), + .regA(rA_timecode_stop0), + .regB(rB_timecode_stop1), + .regC(rC_work_state), .reg_wr_sig(reg_wr_sig), .reg_index (reg_wr_index) @@ -146,24 +126,28 @@ module xsync_internal_generator #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin r0_start_control_mode_reg <= 0; - // r1_stop_control_mode_reg <= 0; r2_genlock_format <= 0; r3_timecode_format <= 0; r4_control_trigger_reg <= 0; - // r5_control_stop_reg <= 0; - r8_timecode_start_time_code <= 0; - r9_timecode_stop_time_code <= 0; + r8_timecode_start0 <= 0; + r9_timecode_start1 <= 0; + rA_timecode_stop0 <= 0; + rB_timecode_stop1 <= 0; + // rC_work_state <= 0; end else begin if (reg_wr_sig) begin case (reg_wr_index) - 0: r0_start_control_mode_reg <= wr_data; - // 1: r1_stop_control_mode_reg <= wr_data; - 2: r2_genlock_format <= wr_data; - 3: r3_timecode_format <= wr_data; - 4: r4_control_trigger_reg <= wr_data; - // 5: r5_control_stop_reg <= wr_data; - 8: r8_timecode_start_time_code <= wr_data; - 9: r9_timecode_stop_time_code <= wr_data; + 31'h0: r0_start_control_mode_reg <= wr_data; + 31'h2: r2_genlock_format <= wr_data; + 31'h3: r3_timecode_format <= wr_data; + 31'h4: r4_control_trigger_reg <= wr_data; + 31'h8: r8_timecode_start0 <= wr_data; + 31'h9: r9_timecode_start1 <= wr_data; + 31'hA: rA_timecode_stop0 <= wr_data; + 31'hB: rB_timecode_stop1 <= wr_data; + // 31'hC: rC_work_state <= wr_data; + default: begin + end endcase end end @@ -176,13 +160,15 @@ module xsync_internal_generator #( // 2.外部触发启动 // 3.TIMECODE触发启动 - // 0.寄存器触发 - // 1.外部TIMECODE触发 - // 2.外部TTL输入1_高电平触发 - // 3.外部TTL输入2_高电平触发 - // 4.外部TTL输入3_高电平触发 - // 5.外部TTL输入4_高电平触发 + // 0.寄存器触发,启动停止 + // 1.外部TIMECODE触发启动,寄存器控制停止 + // 2.外部TTL输入1_高电平触发,低电平停止 + // 3.外部TTL输入2_高电平触发,低电平停止 + // 4.外部TTL输入3_高电平触发,低电平停止 + // 5.外部TTL输入4_高电平触发,低电平停止 // + + zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi ( .chooseindex(r0_start_control_mode_reg), //in @@ -198,17 +184,32 @@ module xsync_internal_generator #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin start_sig <= 0; + rC_work_state <= 0; end else begin case (r0_start_control_mode_reg[31:0]) 0: begin //寄存器控制启动 + + if (reg_wr_sig && reg_wr_index == CTRL_REG_INDEX) begin + if (wr_data[0] == 1) begin + rC_work_state[0] <= 1; + end else begin + rC_work_state[0] <= 0; + end + end + end 1: begin //TIMECODE触发 + end 2, 3, 4, 5: begin //外部电平控制 - + if (ext_ttlinx_module_raw_sig == 1) begin + rC_work_state[0] <= 1; + end else begin + rC_work_state[0] <= 0; + end end default: begin end @@ -227,7 +228,7 @@ module xsync_internal_generator #( ) genlock ( .clk(clk), .rst_n(rst_n), - .ctrl_sig(out_working_flag), + .ctrl_sig(out_en_flag), .genlock_fps2397_clk(genlock_fps2397_clk), .genlock_fps2398_clk(genlock_fps2398_clk), .genlock_fps2400_clk(genlock_fps2400_clk), @@ -259,37 +260,6 @@ module xsync_internal_generator #( /******************************************************************************* * smpte_timecode_clk_generator * *******************************************************************************/ - // - // TimeCode 基础控制信号生成 - // 1 - // - // - - - // module timecode_generator #( - // parameter SYS_CLOCK_FREQ = 10000000 - // ) ( - // input clk, //clock input - // input rst_n, //asynchronous reset input, low active - - // input [31:0] timecode_format, - - // input timecode0_wen, - // input [31:0] timecode0, - // input timecode1_wen, - // input [31:0] timecode1, - - // input en, - - // output wire out_timecode_serial_data, - // output wire out_trigger_sig, - // output wire [31:0] out_timecode0, - // output wire [31:0] out_timecode1 - // ); - - - // r6_timecode0 - // r7_timecode1 timecode_generator #( .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) @@ -307,7 +277,7 @@ module xsync_internal_generator #( .timecode0_export(r6_timecode0), .timecode1_export(r7_timecode1), - .en(en), + .en(out_en_flag), .out_timecode_serial_data(out_timecode_serial_sig), .out_trigger_sig(out_timecode_tirgger_sig), @@ -315,26 +285,5 @@ module xsync_internal_generator #( .out_timecode1(out_timecode_sig[63:32]) ); - // internal_timecode_generator #( - // .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - // ) internal_timecode_generator ( - // .clk(clk), - // .rst_n(rst_n), - // .ctrl_sig(out_working_flag), - - // .timecode_format(r3_timecode_format), - - // //寄存器读写接口 - // .timecode_tc_wr_data(wr_data), - // .timecode_tc_wr_en (reg_wr_index == 6), - // .out_timecode_tc_reg(r6_timecode0), - - // .timecode_uc_wr_data(wr_data), - // .timecode_uc_wr_en (reg_wr_index == 7), - // .out_timecode_uc_reg(r7_timecode1), - - // .out_timecode_tirgger_sig(out_timecode_tirgger_sig) - // ); - // assign out_timecode_sig = {r6_timecode0, r7_timecode1}; endmodule