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fpga_led_test
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spi ok

master
zhaohe 2 years ago
parent
c6028d9bfd
commit
9d143fb497
10 changed files with 114 additions and 84 deletions
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  1. 80
      led_test.pds
  2. 2
      source/src/rd_data_router.v
  3. 12
      source/src/spi_reg_reader.v
  4. 27
      source/src/top.v
  5. 12
      source/src/zutils/zutils_edge_detecter.v
  6. 2
      source/src/zutils/zutils_multiplexer_16t1.v
  7. 2
      source/src/zutils/zutils_pwm_generator.v
  8. 37
      source/src/zutils/zutils_register.v
  9. 22
      source/src/zutils/zutils_reset_sig_gen.v
  10. 2
      source/src/zutils/zutils_signal_filter.v

80
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan 8 21:31:11 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan 8 22:23:17 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,11 +19,11 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-01-08T21:28:52")
(_timespec "2024-01-08T22:21:53")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
(_timespec "2024-01-08T17:40:40")
(_timespec "2024-01-08T22:12:49")
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
@ -31,11 +31,11 @@
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
(_timespec "2024-01-08T17:41:58")
(_timespec "2024-01-08T22:12:54")
)
(_file "source/src/zutils/zutils_register.v"
(_format verilog)
(_timespec "2024-01-08T19:03:09")
(_timespec "2024-01-08T22:10:43")
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
@ -47,7 +47,7 @@
)
(_file "source/src/zutils/zutils_signal_filter.v"
(_format verilog)
(_timespec "2024-01-08T17:44:10")
(_timespec "2024-01-08T22:15:39")
)
(_file "source/src/zutils/zutils_clk_parser.v"
(_format verilog)
@ -55,19 +55,23 @@
)
(_file "source/src/zutils/zutils_multiplexer_16t1.v"
(_format verilog)
(_timespec "2024-01-08T17:42:43")
(_timespec "2024-01-08T22:15:04")
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-01-08T20:10:41")
(_timespec "2024-01-08T22:10:21")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
(_timespec "2024-01-08T19:25:32")
(_timespec "2024-01-08T22:15:09")
)
(_file "source/src/rd_data_router.v"
(_format verilog)
(_timespec "2024-01-08T18:48:27")
(_timespec "2024-01-08T22:15:00")
)
(_file "source/src/zutils/zutils_reset_sig_gen.v"
(_format verilog)
(_timespec "2024-01-08T22:22:50")
)
)
)
@ -85,7 +89,7 @@
(_input
(_file "led_test.fdc"
(_format fdc)
(_timespec "2024-01-08T18:10:50")
(_timespec "2024-01-08T21:48:05")
)
)
)
@ -109,7 +113,7 @@
)
(_file "source/test/test_top.v" + "test_top:"
(_format verilog)
(_timespec "2024-01-08T19:17:37")
(_timespec "2024-01-08T22:10:21")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
@ -128,17 +132,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-01-08T21:30:52")
(_timespec "2024-01-08T22:22:53")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-01-08T21:30:52")
(_timespec "2024-01-08T22:22:53")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-01-08T21:30:52")
(_timespec "2024-01-08T22:22:53")
)
)
)
@ -154,21 +158,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-01-08T21:30:55")
(_timespec "2024-01-08T22:22:56")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-01-08T21:30:55")
(_timespec "2024-01-08T22:22:57")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-01-08T21:30:55")
(_timespec "2024-01-08T22:22:57")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-01-08T21:30:55")
(_timespec "2024-01-08T22:22:57")
)
)
)
@ -189,21 +193,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-01-08T21:30:57")
(_timespec "2024-01-08T22:22:59")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-01-08T21:30:57")
(_timespec "2024-01-08T22:22:59")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-01-08T21:30:57")
(_timespec "2024-01-08T22:22:59")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-01-08T21:30:57")
(_timespec "2024-01-08T22:22:59")
)
)
)
@ -212,7 +216,7 @@
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-01-08T21:30:57")
(_timespec "2024-01-08T22:22:59")
)
)
)
@ -226,33 +230,33 @@
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-01-08T21:31:02")
(_timespec "2024-01-08T22:23:07")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-01-08T21:31:02")
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-01-08T21:31:02")
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-01-08T21:31:02")
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-01-08T21:31:01")
(_timespec "2024-01-08T22:23:05")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-01-08T21:31:02")
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-01-08T21:31:03")
(_timespec "2024-01-08T22:23:08")
)
)
)
@ -268,17 +272,17 @@
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-01-08T21:31:06")
(_timespec "2024-01-08T22:23:11")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-01-08T21:31:06")
(_timespec "2024-01-08T22:23:11")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-01-08T21:31:06")
(_timespec "2024-01-08T22:23:11")
)
)
)
@ -302,19 +306,19 @@
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-01-08T21:31:10")
(_timespec "2024-01-08T22:23:16")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-01-08T21:31:10")
(_timespec "2024-01-08T22:23:16")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-01-08T21:31:10")
(_timespec "2024-01-08T22:23:16")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-01-08T21:31:11")
(_timespec "2024-01-08T22:23:17")
)
)
)

2
source/src/rd_data_router.v
View File

@ -27,7 +27,7 @@ module rd_data_router (
output reg [31:0] rd_data_out
);
initial rd_data_out = 0;
// initial rd_data_out = 0;
// wire [31:0] addr_8 = addr >> 8;
wire [31:0] addr_group;
assign addr_group = addr & 31'hFFFF_FFF0;

12
source/src/spi_reg_reader.v
View File

@ -22,12 +22,12 @@ module spi_reg_reader (
parameter STATE_WRITE_REG = 5;
parameter ADDRESS_WIDTH_BYTE_NUM = 2;
initial begin
addr = 0;
wr_data = 0;
wr_en = 0;
spi_tx_pin = 0;
end
// initial begin
// addr = 0;
// wr_data = 0;
// wr_en = 0;
// spi_tx_pin = 0;
// end
zutils_signal_filter #(

27
source/src/top.v
View File

@ -107,6 +107,7 @@ module Top (
localparam HARDWARE_TEST_MODE = 1;
SPLL spll (
.clkin1(sys_clk), // input
.pll_lock(pll_lock), // output
@ -115,13 +116,19 @@ module Top (
.clkout2(sys_clk_5m) // output
);
zutils_reset_sig_gen reset_sig_gen_inst (
.clk(sys_clk),
.rst_n(rst_n),
.rst_n_out(sys_rst_n)
);
/*******************************************************************************
* 调试器 *
*******************************************************************************/
// wire [6:0] trig0_i;
// JtagHubIst jtag_hub_ist (
// .resetn_i(rst_n), // input
// .resetn_i(sys_rst_n), // input
// .drck_o (drck_o), // output
// .hub_tdi (hub_tdi), // output
// .capt_o (capt_o), // output
@ -140,7 +147,7 @@ module Top (
// .conf_sel(conf_sel[0]), // input
// .drck_in (drck_o), // input
// .clk (sys_clk), // input
// .resetn_i(rst_n), // input
// .resetn_i(sys_rst_n), // input
// .trig0_i (trig0_i)
// );
@ -152,7 +159,7 @@ module Top (
// .PERIOD_COUNT(10000000)
// ) core_board_debug_led_inst (
// .clk(sys_clk),
// .rst_n(rst_n),
// .rst_n(sys_rst_n),
// .debug_led(core_board_debug_led)
// );
@ -166,7 +173,7 @@ module Top (
wire [31:0] reg_reader_bus_rd_data;
spi_reg_reader spi_reg_reader_inst (
.clk (sys_clk),
.rst_n(rst_n),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
@ -199,8 +206,6 @@ module Top (
/*******************************************************************************
* TEST_SPI_REG *
*******************************************************************************/
@ -224,7 +229,7 @@ module Top (
.REGF_INIT(31'hffff_ffff)
) test_reg (
.clk(sys_clk),
.rst_n(rst_n),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
@ -244,7 +249,7 @@ module Top (
// .ID(1)
// ) ttl_output_1 (
// .clk (sys_clk),
// .rst_n(rst_n),
// .rst_n(sys_rst_n),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),
@ -263,7 +268,7 @@ module Top (
// .ID(2)
// ) ttl_output_2 (
// .clk (sys_clk),
// .rst_n(rst_n),
// .rst_n(sys_rst_n),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),
@ -282,7 +287,7 @@ module Top (
// .ID(3)
// ) ttl_output_3 (
// .clk (sys_clk),
// .rst_n(rst_n),
// .rst_n(sys_rst_n),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),
@ -301,7 +306,7 @@ module Top (
// .ID(4)
// ) ttl_output_4 (
// .clk (sys_clk),
// .rst_n(rst_n),
// .rst_n(sys_rst_n),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),

12
source/src/zutils/zutils_edge_detecter.v
View File

@ -8,12 +8,12 @@ module zutils_edge_detecter (
output reg in_signal_edge
);
initial begin
in_signal_last = 0;
in_signal_rising_edge = 0;
in_signal_falling_edge = 0;
in_signal_edge = 0;
end
// initial begin
// in_signal_last = 0;
// in_signal_rising_edge = 0;
// in_signal_falling_edge = 0;
// in_signal_edge = 0;
// end

2
source/src/zutils/zutils_multiplexer_16t1.v
View File

@ -4,7 +4,7 @@ module zutils_multiplexer_16t1 (
output reg signalout
);
initial signalout = 0;
// initial signalout = 0;
always @(*) begin
case (chooseindex)

2
source/src/zutils/zutils_pwm_generator.v
View File

@ -8,7 +8,7 @@ module zutils_pwm_generator #(
);
initial output_signal = 0;
// initial output_signal = 0;
localparam COUNT = SYS_CLOCK_FREQ / OUTPUT_FREQ;
reg [31:0] counter = 0;

37
source/src/zutils/zutils_register.v
View File

@ -66,26 +66,25 @@ module zutils_register16 #(
assign regE = data[14];
assign regF = data[15];
initial begin
data[0] <= REG0_INIT;
data[1] <= REG1_INIT;
data[2] <= REG2_INIT;
data[3] <= REG3_INIT;
data[4] <= REG4_INIT;
data[5] <= REG5_INIT;
data[6] <= REG6_INIT;
data[7] <= REG7_INIT;
data[8] <= REG8_INIT;
data[9] <= REG9_INIT;
data[10] <= REGA_INIT;
data[11] <= REGB_INIT;
data[12] <= REGC_INIT;
data[13] <= REGD_INIT;
data[14] <= REGE_INIT;
data[15] <= REGF_INIT;
end
// initial begin
// data[0] <= REG0_INIT;
// data[1] <= REG1_INIT;
// data[2] <= REG2_INIT;
// data[3] <= REG3_INIT;
// data[4] <= REG4_INIT;
// data[5] <= REG5_INIT;
// data[6] <= REG6_INIT;
// data[7] <= REG7_INIT;
// data[8] <= REG8_INIT;
// data[9] <= REG9_INIT;
// data[10] <= REGA_INIT;
// data[11] <= REGB_INIT;
// data[12] <= REGC_INIT;
// data[13] <= REGD_INIT;
// data[14] <= REGE_INIT;
// data[15] <= REGF_INIT;
// end
integer i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data[0] <= REG0_INIT;

22
source/src/zutils/zutils_reset_sig_gen.v
View File

@ -0,0 +1,22 @@
module zutils_reset_sig_gen (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
output reg rst_n_out
);
reg [31:0] counter = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
counter <= 0;
rst_n_out <= 0;
end else begin
if (counter < 10) begin
rst_n_out <= 0;
counter <= counter + 1;
end else if (counter == 10) begin
counter <= counter;
rst_n_out <= 1;
end
end
end
endmodule

2
source/src/zutils/zutils_signal_filter.v
View File

@ -6,7 +6,7 @@ module zutils_signal_filter #(
input wire in,
output reg out
);
initial out = 0;
// initial out = 0;
reg [31:0] counter = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin

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