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fpga_led_test
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zhaohe 2 years ago
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e933ae778a
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aca8787430
2 changed files with 48 additions and 45 deletions
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  1. 56
      led_test.pds
  2. 37
      source/src/top.v

56
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Jan 11 20:42:45 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Jan 11 22:38:56 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-01-11T20:39:36")
(_timespec "2024-01-11T22:37:23")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -207,17 +207,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-01-11T20:41:02")
(_timespec "2024-01-11T22:37:29")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-01-11T20:41:00")
(_timespec "2024-01-11T22:37:28")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-01-11T20:41:02")
(_timespec "2024-01-11T22:37:29")
)
)
)
@ -233,21 +233,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-01-11T20:41:20")
(_timespec "2024-01-11T22:37:48")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-01-11T20:41:20")
(_timespec "2024-01-11T22:37:49")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-01-11T20:41:21")
(_timespec "2024-01-11T22:37:50")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-01-11T20:41:21")
(_timespec "2024-01-11T22:37:50")
)
)
)
@ -268,21 +268,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-01-11T20:41:25")
(_timespec "2024-01-11T22:37:55")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-01-11T20:41:24")
(_timespec "2024-01-11T22:37:54")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-01-11T20:41:25")
(_timespec "2024-01-11T22:37:55")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-01-11T20:41:25")
(_timespec "2024-01-11T22:37:55")
)
)
)
@ -291,7 +291,7 @@
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-01-11T20:41:25")
(_timespec "2024-01-11T22:37:55")
)
)
)
@ -305,33 +305,33 @@
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-01-11T20:42:07")
(_timespec "2024-01-11T22:38:36")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-01-11T20:42:07")
(_timespec "2024-01-11T22:38:36")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-01-11T20:42:07")
(_timespec "2024-01-11T22:38:36")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-01-11T20:42:07")
(_timespec "2024-01-11T22:38:36")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-01-11T20:41:51")
(_timespec "2024-01-11T22:38:19")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-01-11T20:42:07")
(_timespec "2024-01-11T22:38:36")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-01-11T20:42:07")
(_timespec "2024-01-11T22:38:36")
)
)
)
@ -347,17 +347,17 @@
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-01-11T20:42:13")
(_timespec "2024-01-11T22:38:42")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-01-11T20:42:13")
(_timespec "2024-01-11T22:38:42")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-01-11T20:42:14")
(_timespec "2024-01-11T22:38:42")
)
)
)
@ -381,19 +381,19 @@
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-01-11T20:42:44")
(_timespec "2024-01-11T22:38:55")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-01-11T20:42:44")
(_timespec "2024-01-11T22:38:55")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-01-11T20:42:44")
(_timespec "2024-01-11T22:38:55")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-01-11T20:42:45")
(_timespec "2024-01-11T22:38:56")
)
)
)

37
source/src/top.v
View File

@ -493,7 +493,7 @@ module Top (
.REG_ADD_OFF_GENLOCK_OUT(REG_ADD_OFF_GENLOCK_OUT),
.REG_ADD_OFF_CAMERA_SYNC_OUT(REG_ADD_OFF_CAMERA_SYNC_OUT),
.REG_ADD_OFF_DEBUGER(REG_ADD_OFF_DEBUGER)
) rd_data_router_inst (
.addr(reg_reader_bus_addr),
@ -531,24 +531,27 @@ module Top (
// output reg timecode_out_headphone_select, // 电平选择 0line,1:mic
// output reg timecode_out_headphone_state_led
assign debug_signal_output[0] = spi2_cs_pin;
assign debug_signal_output[1] = spi2_clk_pin;
assign debug_signal_output[2] = spi2_rx_pin;
assign debug_signal_output[3] = spi2_tx_pin;
assign debug_signal_output[4] = sync_ttl_out1;
assign debug_signal_output[5] = sync_ttl_out2;
assign debug_signal_output[6] = sync_ttl_out3;
assign debug_signal_output[7] = sync_ttl_out4;
assign debug_signal_output[8] = stm32if_timecode_sync_out;
assign debug_signal_output[9] = timecode_out_bnc;
assign debug_signal_output[10] = timecode_out_headphone;
assign debug_signal_output[11] = timecode_out_bnc_select;
assign debug_signal_output[12] = timecode_out_headphone_select;
assign debug_signal_output[13] = 0;
assign debug_signal_output[14] = 0;
assign debug_signal_output[15] = 0;
assign debug_signal_output[0] = sync_ttl_out1;
assign debug_signal_output[1] = sync_ttl_out2;
assign debug_signal_output[2] = sync_ttl_out3;
assign debug_signal_output[3] = sync_ttl_out4;
assign debug_signal_output[4] = stm32if_timecode_sync_out;
assign debug_signal_output[5] = timecode_out_bnc;
assign debug_signal_output[6] = timecode_out_headphone;
assign debug_signal_output[7] = genlock_in_hsync;
assign debug_signal_output[8] = genlock_in_vsync;
assign debug_signal_output[9] = genlock_in_fsync;
assign debug_signal_output[10] = sync_ttl_in1;
assign debug_signal_output[11] = sync_ttl_in2;
assign debug_signal_output[12] = sync_ttl_in3;
assign debug_signal_output[13] = sync_ttl_in4;
assign debug_signal_output[14] = timecode_headphone_in;
assign debug_signal_output[15] = timecode_bnc_in;
assign core_board_debug_led = 1;
assign genlock_in_state_led = 1;
endmodule
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