From bf430d67b599291ac6dd37efa6c760e90c2dad28 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sun, 31 Dec 2023 15:14:27 +0800 Subject: [PATCH] update --- led_test.pds | 96 +++++++++-- source/src/des_ttl_generator.v | 63 ++++--- source/src/spi_reg_reader.v.bak | 259 ----------------------------- source/src/src_timecode.v | 208 +++++++++++++++++++++++ source/src/top.v | 33 ++-- source/src/zutils/zutils_edge_detecter.v | 45 +++++ source/src/zutils/zutils_pluse_generator.v | 29 ++++ source/src/zutils/zutils_register.v | 31 ++++ 8 files changed, 446 insertions(+), 318 deletions(-) delete mode 100644 source/src/spi_reg_reader.v.bak create mode 100644 source/src/zutils/zutils_edge_detecter.v create mode 100644 source/src/zutils/zutils_pluse_generator.v create mode 100644 source/src/zutils/zutils_register.v diff --git a/led_test.pds b/led_test.pds index 7929108..6834ce7 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Dec 30 17:32:33 2023") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Dec 31 15:14:14 2023") (_version "1.0.5") (_status "initial") (_project @@ -27,7 +27,7 @@ ) (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2023-12-30T12:39:05") + (_timespec "2023-12-31T15:13:50") ) (_file "source/src/uart_tx.v" (_format verilog) @@ -55,11 +55,23 @@ ) (_file "source/src/src_timecode.v" (_format verilog) - (_timespec "2023-12-30T16:15:29") + (_timespec "2023-12-30T20:50:11") ) (_file "source/src/des_ttl_generator.v" (_format verilog) - (_timespec "2023-12-30T17:32:32") + (_timespec "2023-12-31T15:12:53") + ) + (_file "source/src/zutils/zutils_pluse_generator.v" + (_format verilog) + (_timespec "2023-12-31T14:50:20") + ) + (_file "source/src/zutils/zutils_edge_detecter.v" + (_format verilog) + (_timespec "2023-12-31T15:00:01") + ) + (_file "source/src/zutils/zutils_register.v" + (_format verilog) + (_timespec "2023-12-31T14:53:25") ) ) ) @@ -119,21 +131,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2023-12-30T14:43:56") + (_timespec "2023-12-31T15:14:05") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2023-12-30T14:43:56") + (_timespec "2023-12-31T15:14:04") ) (_file "compile/cmr.db" (_format text) - (_timespec "2023-12-30T14:43:56") + (_timespec "2023-12-31T15:14:05") ) ) ) @@ -143,27 +155,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2023-12-30T14:53:59") + (_timespec "2023-12-31T15:14:07") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2023-12-30T14:53:59") + (_timespec "2023-12-31T15:14:07") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2023-12-30T14:53:59") + (_timespec "2023-12-31T15:14:07") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2023-12-30T14:53:59") + (_timespec "2023-12-31T15:14:07") ) ) ) @@ -180,14 +192,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2023-12-31T15:14:09") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2023-12-31T15:14:09") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2023-12-31T15:14:09") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2023-12-31T15:14:09") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2023-12-15T20:24:09") + (_timespec "2023-12-31T15:14:09") ) ) ) @@ -197,7 +229,39 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2023-12-31T15:14:13") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2023-12-31T15:14:13") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2023-12-31T15:14:13") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2023-12-31T15:14:12") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2023-12-31T15:14:12") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2023-12-31T15:14:13") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2023-12-31T15:14:14") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) diff --git a/source/src/des_ttl_generator.v b/source/src/des_ttl_generator.v index b3f5012..01d5dcc 100644 --- a/source/src/des_ttl_generator.v +++ b/source/src/des_ttl_generator.v @@ -1,3 +1,6 @@ +// `include "zutils/zutils_edge_detecter.v" +// `include "zutils/zutils_pluse_generator.v" +// `include "zutils/zutils_register.v" module des_ttl_generator #( parameter REG_START_ADD = 0 ) ( @@ -5,7 +8,7 @@ module des_ttl_generator #( input rst_n, //asynchronous reset input, low active //regbus interface - output reg [31:0] addr, + output [31:0] addr, input [31:0] wr_data, input wr_en, @@ -50,19 +53,39 @@ module des_ttl_generator #( /******************************************************************************* * 寄存器读写 * *******************************************************************************/ - parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 - reg [31:0] register[REG_START_ADD:REG_END_ADD]; - integer i; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - for (i = 0; i < ADD_NUM; i = i + 1) begin - register[i] <= 0; - end - end else begin - if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; - end - end - assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; + // parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 + // reg [31:0] register[REG_START_ADD:REG_END_ADD]; + // integer i; + // always @(posedge clk or negedge rst_n) begin + // if (!rst_n) begin + // for (i = 0; i < ADD_NUM; i = i + 1) begin + // register[i] <= 0; + // end + // end else begin + // if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; + // end + // end + // assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; + + + + zutils_register #( + .REG_START_ADD(REG_START_ADD), + .ADD_NUM(5) + ) _register ( + .clk(clk), + .rst_n(rst_n), + .addr(addr), + .wr_data(wr_data), + .wr_en(wr_en), + .rd_data(rd_data) + ); + + // zutils_edge_detecter _signal_in ( + // .clk(clk), + // .rst_n(rst_n), + // .signal_in(signal_in) + // ); @@ -82,16 +105,16 @@ module des_ttl_generator #( *******************************************************************************/ // 电平计数 reg [31:0] signal_output_duration_cnt; - assign signal_src_trigger = (register[REG_PULSE_MODE_RISE_FALL_ADD] == 0) ? (signal_in_a & ~signal_in_b) : (~signal_in_a & signal_in_b); + assign signal_src_trigger = (_register.data[REG_PULSE_MODE_RISE_FALL_ADD] == 0) ? (signal_in_a & ~signal_in_b) : (~signal_in_a & signal_in_b); // 通过计数输出波形 - assign ttl_after_process_output = (signal_output_duration_cnt < register[REG_PULSE_MODE_VALID_LEN_ADD]) ? 1 : 0; + assign ttl_after_process_output = (signal_output_duration_cnt < _register.data[REG_PULSE_MODE_VALID_LEN_ADD]) ? 1 : 0; // 脉冲计数 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin signal_output_duration_cnt <= 0; end else begin // 脉冲模式 - if (register[REG_FUNC_ADD] == 1) begin + if (_register.data[REG_FUNC_ADD] == 1) begin if (signal_src_trigger == 1) begin signal_output_duration_cnt <= 0; end else begin @@ -108,12 +131,12 @@ module des_ttl_generator #( *******************************************************************************/ reg ttloutput; always @(*) begin - case (register[REG_FUNC_ADD]) + case (_register.data[REG_FUNC_ADD]) 0: begin - ttloutput = (register[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_origin_output : !ttl_origin_output; + ttloutput = (_register.data[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_origin_output : !ttl_origin_output; end 1: begin - ttloutput = (register[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_after_process_output : !ttl_after_process_output; + ttloutput = (_register.data[REG_OUTPUT_POLARITY_ADD][0] == 0) ? ttl_after_process_output : !ttl_after_process_output; end default: ttloutput = 0; endcase diff --git a/source/src/spi_reg_reader.v.bak b/source/src/spi_reg_reader.v.bak deleted file mode 100644 index cea96ee..0000000 --- a/source/src/spi_reg_reader.v.bak +++ /dev/null @@ -1,259 +0,0 @@ -module spi_reg_reader ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //regbus interface - output reg [31:0] addr, - output reg [31:0] wr_data, - output reg wr_en, - input wire [31:0] rd_data, //received serial data - // - input wire spi_cs_pin, - input wire spi_clk_pin, - input wire spi_rx_pin, - output reg spi_tx_pin -); - - parameter STATE_IDLE = 0; - parameter STATE_RECEIVE_ADD = 1; - parameter STATE_READ_REG = 2; - parameter STATE_TRANSMIT_DATA = 3; - parameter STATE_RECEIVE_DATA = 4; - parameter STATE_WRITE_REG = 5; - parameter ADDRESS_WIDTH_BYTE_NUM = 2; - - - // - // 捕获SPI_CS的下降沿 和 SPI_CLK的上升沿 - // detect: - // spi_cs_negedge_tri - // spi_clk_posedge_tri - // - - reg spi_cs_last_state = 0; - reg spi_clk_last_state = 0; - assign spi_clk_posedge_tri = spi_clk_pin & ~spi_clk_last_state; - assign spi_clk_negedge_tri = ~spi_clk_pin & spi_clk_last_state; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - spi_cs_last_state <= 1; - spi_clk_last_state <= 1; - end else begin - spi_cs_last_state <= spi_cs_pin; - spi_clk_last_state <= spi_clk_pin; - end - end - - - /******************************************************************************* - * SPI数据解析，及其部分状态更新 * - *******************************************************************************/ - - // - // - // - // cs : ----______________________________________________ - // clk : ----------____----____----____----____----____---- - // bitcnt : 0 1 2 ... 7 0 - // rx : . . . . . - // tx : <======><======><======><======><======> - // valid : . - // byte_cnt: 0 1 - // - - - reg [7:0] bit_cnt = 0; - reg first_edge = 1; - // first_edge 状态更新 - // 1:在spi_cs下降沿时候更新为0 - // 2:复位时候更新为1 - // bit_cnt 状态更新 - // 1:在spi_clk下降沿时候更新 - // 2:first_edge == 1时候更新 - // - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - bit_cnt <= 0; - first_edge <= 1; - end else begin - if (spi_cs_pin) begin - bit_cnt <= 0; - first_edge <= 1; - end else begin - if (first_edge) begin - bit_cnt <= 0; - first_edge <= 0; - end else begin - if (spi_clk_negedge_tri) begin - if (bit_cnt == 7) bit_cnt <= 0; - else bit_cnt <= bit_cnt + 1; - end - end - end - end - end - - - // - // byte_cnt - // 1:在spi_clk下降沿时候更新 - // 2:在bit_cnt == 7时候更新 - // - reg [7:0] spi_byte_cnt = 0; //byte_cnt - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - spi_byte_cnt <= 0; - end else begin - if (spi_cs_pin) begin - spi_byte_cnt <= 0; - end else begin - if (spi_clk_negedge_tri && bit_cnt == 7) begin - spi_byte_cnt <= spi_byte_cnt + 1; - end - end - end - end - - // - // spi_tx_1byte_data 发送 - // - reg [7:0] spi_tx_1byte_data = 0; - always @(*) begin - spi_tx_pin <= spi_tx_1byte_data[bit_cnt]; - end - - - // - // spi_rx_1byte_data - // spi_rx_1byte_data_valid - // - reg [7:0] spi_rx_1byte_data = 0; - reg spi_rx_1byte_data_valid = 0; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - spi_rx_1byte_data <= 0; - spi_rx_1byte_data_valid <= 0; - end else begin - if (spi_cs_pin) begin - spi_rx_1byte_data <= 0; - spi_rx_1byte_data_valid <= 0; - end else begin - - if (spi_clk_posedge_tri) begin - spi_rx_1byte_data[bit_cnt] <= spi_rx_pin; - end - - if (spi_clk_negedge_tri && bit_cnt == 7) spi_rx_1byte_data_valid <= 1; - else spi_rx_1byte_data_valid <= 0; - - end - end - end - - /******************************************************************************* - * 缓存接收到的数据 * - *******************************************************************************/ - - - reg [7:0] spi_rx_data_cache [0:ADDRESS_WIDTH_BYTE_NUM+4-1] = 0; - reg [7:0] rx_byte_count = 0; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - rx_byte_count <= 0; - spi_rx_data_cache[0] <= 0; - spi_rx_data_cache[1] <= 0; - spi_rx_data_cache[2] <= 0; - spi_rx_data_cache[3] <= 0; - spi_rx_data_cache[4] <= 0; - spi_rx_data_cache[5] <= 0; - end else begin - if (spi_cs_pin) begin - // 失能状态 - rx_byte_count <= 0; - spi_rx_data_cache[0] <= 0; - spi_rx_data_cache[1] <= 0; - spi_rx_data_cache[2] <= 0; - spi_rx_data_cache[3] <= 0; - spi_rx_data_cache[4] <= 0; - spi_rx_data_cache[5] <= 0; - end else begin - // 选中状态 - if (spi_rx_1byte_data_valid) begin - rx_byte_count <= rx_byte_count + 1; - if (rx_byte_count < ADDRESS_WIDTH_BYTE_NUM + 4) begin - spi_rx_data_cache[rx_byte_count] <= spi_rx_1byte_data; - end - end - end - end - end - - - - /******************************************************************************* - * 自动设置SPI需要发送的数据 spi_tx_1byte_data * - *******************************************************************************/ - always @(*) begin - case (spi_byte_cnt) - ADDRESS_WIDTH_BYTE_NUM + 0: spi_tx_1byte_data <= rd_data[7:0]; - ADDRESS_WIDTH_BYTE_NUM + 1: spi_tx_1byte_data <= rd_data[15:8]; - ADDRESS_WIDTH_BYTE_NUM + 2: spi_tx_1byte_data <= rd_data[23:16]; - ADDRESS_WIDTH_BYTE_NUM + 3: spi_tx_1byte_data <= rd_data[31:24]; - default: spi_tx_1byte_data <= 0; - endcase - end - - /******************************************************************************* - * 自动设置addr数值 * - *******************************************************************************/ - always @(*) begin - case (ADDRESS_WIDTH_BYTE_NUM) - 0: begin - addr[6:0] <= spi_rx_data_cache[0][6:0]; - end - 1: begin - addr[7:0] <= spi_rx_data_cache[0][7:0]; - addr[14:8] <= spi_rx_data_cache[1][6:0]; - end - 2: begin - addr[7:0] <= spi_rx_data_cache[0][7:0]; - addr[15:8] <= spi_rx_data_cache[1][7:0]; - addr[22:16] <= spi_rx_data_cache[2][6:0]; - end - 3: begin - addr[7:0] <= spi_rx_data_cache[0][7:0]; - addr[15:8] <= spi_rx_data_cache[1][7:0]; - addr[23:16] <= spi_rx_data_cache[2][7:0]; - addr[30:24] <= spi_rx_data_cache[3][6:0]; - end - endcase - end - - /******************************************************************************* - * wr_data * - *******************************************************************************/ - always @(*) begin - wr_data[7:0] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM]; - wr_data[15:8] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+1]; - wr_data[23:16] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+2]; - wr_data[31:24] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+3]; - end - - /******************************************************************************* - * wr_en * - *******************************************************************************/ - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - wr_en <= 0; - end else begin - if (!spi_cs_pin && spi_clk_negedge_tri && spi_byte_cnt == ADDRESS_WIDTH_BYTE_NUM + 4) begin - wr_en <= 1; - end else begin - wr_en <= 0; - end - end - end - - - -endmodule diff --git a/source/src/src_timecode.v b/source/src/src_timecode.v index e69de29..7d08d49 100644 --- a/source/src/src_timecode.v +++ b/source/src/src_timecode.v @@ -0,0 +1,208 @@ +module src_timecode_parser #( + parameter REG_START_ADD = 0 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //regbus interface + output reg [31:0] addr, + input [31:0] wr_data, + input wr_en, + + inout wire [31:0] rd_data, //received serial data + // 输入 + input timecode_signal_in, + //输出 + output wire timecode_signal_orgin_output, //ttl原始数据 + output wire timecode_freq_trigger_signal +); + + /******************************************************************************* + * 寄存器读写 * + *******************************************************************************/ + + // + // @功能: + // 1. 采样TIMECODE信号 + // 2. 转发TIMECODE信号 + // 3. TIMECODE信号成功解析 + // 4. TIMECODE采样计数 + // + // @寄存器列表: + // 地址 读写 默认 描述 + // 0x00 wr 0x0 timecode bit周期 + // 0x01 r 0x0 flag bit[0]:timecode_ready_flag + // 0x02 r 0x0 timecode [31:0] + // 0x03 r 0x0 timecode [63:32] + // 0x04 r 0x0 timecode_ready_signal_pluse_width //识别到一帧timecode信号后，输出一个脉冲信号，用于同步其他模块 + + parameter REG_TIMECODE_BIT_PERIOD_ADD = REG_START_ADD + 0; //timecode bit周期寄存器地址 + + + parameter ADD_NUM = 5; //寄存器数量 + parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 + reg [31:0] register[REG_START_ADD:REG_END_ADD]; + integer i; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + for (i = 0; i < ADD_NUM; i = i + 1) begin + register[i] <= 0; + end + end else begin + if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; + end + end + assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; + + + + // 416us 500us 520us + // 边沿触发--> 采样偏移同步 + // + + // 416us采用 160byte 采样到同步 + // 电平变化修正采样计数 + + // + // 配置: + // 1. 制式 + // 2. + + // 边沿信号捕获 + + + reg [160-1:0] tc_bit_2x; //timecode 每1/2bit + reg [79:0] tc_bit; //timecode 每1bit + reg sample_signal; //采样信号 + reg [31:0] sample_time_cnt; //采样计数 + wire sample_time_calibrate_signal; //采样信号修正器 + reg time_code_signal_edge; //timecode原始信号的边沿信号，即timecode上升沿或者下降沿时，置1 + assign timecode_signal_in_a = timecode_signal_in; // + reg timecode_signal_in_b; // + reg tc_sync_signal_edge; // timecode捕获到同步信号时，置1，此时可以解析timecode信号，并将其存放到寄存中 + + + /******************************************************************************* + * timecode边沿信号捕获 * + *******************************************************************************/ + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + timecode_signal_in_b <= 0; + end else begin + timecode_signal_in_b <= timecode_signal_in_a; + end + end + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + time_code_signal_edge <= 0; + end else begin + if (timecode_signal_in_a != timecode_signal_in_b) begin + time_code_signal_edge <= 1; + end else begin + time_code_signal_edge <= 0; + end + end + end + + assign sample_time_calibrate_signal = time_code_signal_edge; + + + /******************************************************************************* + * BIT信号映射 * + *******************************************************************************/ + // + // 采样点 采样点 采样点 采样点 + // + + + + + // ___------------_______-------- + // 0 1 + // timecode的每个bit要通过两个点进行判断，所以需要2x的采样率 + // + always @(*) begin + for (i = 0; i < 79; i = i + 1) begin + tc_bit[i] = !tc_bit_2x[i*2] & tc_bit_2x[i*2+1]; + end + end + + /******************************************************************************* + * 采样信号生成器 * + *******************************************************************************/ + // + // 1. 当捕获到timecode原始信号的边沿时，校准采样信号计数器 + // 2. 当采样信号计数器到达采样点时，输出采样信号 + // 3. 当采样信号计数器到达2倍采样点时，重置采样信号计数器 + // + assign timecode_sample_cnt_reset_signal = ( + sample_time_calibrate_signal|| + sample_time_cnt >= (register[REG_TIMECODE_BIT_PERIOD_ADD] << 1) + ); + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + sample_time_cnt <= 0; + sample_signal <= 0; + end else begin + if (timecode_sample_cnt_reset_signal) begin + sample_time_cnt <= 0; + sample_signal <= 0; + end else if (sample_time_cnt == register[REG_TIMECODE_BIT_PERIOD_ADD]) begin + sample_time_cnt <= sample_time_cnt + 1; + sample_signal <= 1; + end else begin + sample_time_cnt <= sample_time_cnt + 1; + sample_signal <= 0; + end + end + end + + // + // 根据sample_signal捕获timecode信号 + // + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + tc_bit_2x <= 0; + end else begin + if (sample_signal) begin + tc_bit_2x <= {tc_bit_2x[158:0], timecode_signal_in}; + end else begin + tc_bit_2x <= tc_bit_2x; + end + end + end + + /******************************************************************************* + * tc_sync_signal_edge * + *******************************************************************************/ + // ___------------_______-------- + // 0 1 + // + // 捕获timecode同步信号 + // + // 同步信号 + // 0011_1111_11111_1101 + // 1111_0101__0101_0101__0101_0101__0101_1101 + // + reg [31:0] sync_code_pattern = 32'b1111_0101__0101_0101__0101_0101__0101_1101; + assign tc_sync_signal = (tc_bit == sync_code_pattern); + reg tc_sync_signal_b; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + tc_sync_signal_b <= 0; + end else begin + tc_sync_signal_b <= tc_sync_signal; + + if (tc_sync_signal & !tc_sync_signal_b) begin + tc_sync_signal_edge <= 1; + end else begin + tc_sync_signal_edge <= 0; + end + end + end + + + + + assign timecode_freq_trigger_signal = tc_sync_signal_edge; + + + +endmodule diff --git a/source/src/top.v b/source/src/top.v index 0ceaf20..bc52724 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -14,29 +14,16 @@ module Top ( .clkout0(inclkpll_clk0out) ); - - - monitor_line monitor_line_usb_serial_rx ( - sys_clk, - rst_n, - usb_serial_rx, - test_io[4] - ); - assign test_io[3] = usb_serial_tx; - // assign test_io[3] = inclkpll_clk0out; - - src_ttl_parser src_ttl_parser_inst ( - .clk(), - .rst_n(), - //regbus interface - .addr(), - .wr_data(), - .wr_en(), - .rd_data(), - .ttlin(), - .ttl_origin_data(), - .ttl_after_process_data() - ); +des_ttl_generator des_ttl_generator_inst ( + .clk(sys_clk), + .rst_n(rst_n), + .addr(), + .wr_data(0), + .wr_en(0), + .rd_data(), + .signal_in(1), + .ttloutput(test_io[3]) +); endmodule diff --git a/source/src/zutils/zutils_edge_detecter.v b/source/src/zutils/zutils_edge_detecter.v new file mode 100644 index 0000000..eb63e72 --- /dev/null +++ b/source/src/zutils/zutils_edge_detecter.v @@ -0,0 +1,45 @@ +module zutils_edge_detecter ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + input wire signal_in + +); + + reg signal_in_last = 0; + assign now = signal_in; + assign last = signal_in_last; + + reg rsing_edge_signal; + reg falling_edge_signal; + reg edge_sginal; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + signal_in_last <= 0; + end else begin + signal_in_last <= signal_in; + end + end + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + rsing_edge_signal <= 0; + falling_edge_signal <= 0; + edge_sginal <= 0; + end else begin + if (signal_in_last == 0 && signal_in == 1) begin + rsing_edge_signal <= 1; + falling_edge_signal <= 0; + edge_sginal <= 1; + end else if (signal_in_last == 1 && signal_in == 0) begin + rsing_edge_signal <= 0; + falling_edge_signal <= 1; + edge_sginal <= 1; + end else begin + rsing_edge_signal <= 0; + falling_edge_signal <= 0; + edge_sginal <= 0; + end + end + end +endmodule diff --git a/source/src/zutils/zutils_pluse_generator.v b/source/src/zutils/zutils_pluse_generator.v new file mode 100644 index 0000000..c7a37d3 --- /dev/null +++ b/source/src/zutils/zutils_pluse_generator.v @@ -0,0 +1,29 @@ +module zutils_pluse_generator ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + input wire [31:0] pluse_width, + input wire trigger, + output reg pluse +); + + reg [31:0] counter = 0; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + counter <= 0; + pluse <= 0; + end else begin + if (trigger) begin + counter <= pluse_width; + pluse <= 1; + end else begin + if (counter == 0) begin + pluse <= 0; + end else begin + counter <= counter - 1; + end + end + end + end +endmodule diff --git a/source/src/zutils/zutils_register.v b/source/src/zutils/zutils_register.v new file mode 100644 index 0000000..2406014 --- /dev/null +++ b/source/src/zutils/zutils_register.v @@ -0,0 +1,31 @@ +module zutils_register #( + parameter REG_START_ADD = 0, + parameter ADD_NUM = 10 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //regbus interface + output reg [31:0] addr, + input [31:0] wr_data, + input wr_en, + + inout wire [31:0] rd_data //received serial data +); + + parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 + reg [31:0] data[REG_START_ADD:REG_END_ADD]; + integer i; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + for (i = 0; i < ADD_NUM; i = i + 1) begin + data[i] <= 0; + end + end else begin + if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) data[addr] <= wr_data; + end + end + assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr] : 31'bz; + + +endmodule