8 changed files with 446 additions and 318 deletions
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96led_test.pds
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63source/src/des_ttl_generator.v
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259source/src/spi_reg_reader.v.bak
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208source/src/src_timecode.v
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33source/src/top.v
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45source/src/zutils/zutils_edge_detecter.v
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29source/src/zutils/zutils_pluse_generator.v
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31source/src/zutils/zutils_register.v
@ -1,259 +0,0 @@ |
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module spi_reg_reader ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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//regbus interface |
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output reg [31:0] addr, |
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output reg [31:0] wr_data, |
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output reg wr_en, |
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input wire [31:0] rd_data, //received serial data |
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// |
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input wire spi_cs_pin, |
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input wire spi_clk_pin, |
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input wire spi_rx_pin, |
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output reg spi_tx_pin |
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); |
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parameter STATE_IDLE = 0; |
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parameter STATE_RECEIVE_ADD = 1; |
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parameter STATE_READ_REG = 2; |
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parameter STATE_TRANSMIT_DATA = 3; |
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parameter STATE_RECEIVE_DATA = 4; |
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parameter STATE_WRITE_REG = 5; |
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parameter ADDRESS_WIDTH_BYTE_NUM = 2; |
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// |
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// 捕获SPI_CS的下降沿 和 SPI_CLK的上升沿 |
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// detect: |
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// spi_cs_negedge_tri |
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// spi_clk_posedge_tri |
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// |
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reg spi_cs_last_state = 0; |
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reg spi_clk_last_state = 0; |
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assign spi_clk_posedge_tri = spi_clk_pin & ~spi_clk_last_state; |
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assign spi_clk_negedge_tri = ~spi_clk_pin & spi_clk_last_state; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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spi_cs_last_state <= 1; |
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spi_clk_last_state <= 1; |
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end else begin |
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spi_cs_last_state <= spi_cs_pin; |
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spi_clk_last_state <= spi_clk_pin; |
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end |
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end |
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/******************************************************************************* |
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* SPI数据解析，及其部分状态更新 * |
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*******************************************************************************/ |
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// |
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// |
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// |
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// cs : ----______________________________________________ |
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// clk : ----------____----____----____----____----____---- |
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// bitcnt : 0 1 2 ... 7 0 |
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// rx : . . . . . |
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// tx : <======><======><======><======><======> |
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// valid : . |
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// byte_cnt: 0 1 |
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// |
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reg [7:0] bit_cnt = 0; |
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reg first_edge = 1; |
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// first_edge 状态更新 |
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// 1:在spi_cs下降沿时候更新为0 |
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// 2:复位时候更新为1 |
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// bit_cnt 状态更新 |
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// 1:在spi_clk下降沿时候更新 |
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// 2:first_edge == 1时候更新 |
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// |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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bit_cnt <= 0; |
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first_edge <= 1; |
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end else begin |
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if (spi_cs_pin) begin |
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bit_cnt <= 0; |
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first_edge <= 1; |
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end else begin |
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if (first_edge) begin |
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bit_cnt <= 0; |
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first_edge <= 0; |
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end else begin |
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if (spi_clk_negedge_tri) begin |
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if (bit_cnt == 7) bit_cnt <= 0; |
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else bit_cnt <= bit_cnt + 1; |
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end |
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end |
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end |
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end |
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end |
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// |
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// byte_cnt |
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// 1:在spi_clk下降沿时候更新 |
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// 2:在bit_cnt == 7时候更新 |
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// |
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reg [7:0] spi_byte_cnt = 0; //byte_cnt |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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spi_byte_cnt <= 0; |
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end else begin |
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if (spi_cs_pin) begin |
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spi_byte_cnt <= 0; |
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end else begin |
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if (spi_clk_negedge_tri && bit_cnt == 7) begin |
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spi_byte_cnt <= spi_byte_cnt + 1; |
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end |
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end |
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end |
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end |
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// |
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// spi_tx_1byte_data 发送 |
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// |
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reg [7:0] spi_tx_1byte_data = 0; |
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always @(*) begin |
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spi_tx_pin <= spi_tx_1byte_data[bit_cnt]; |
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end |
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// |
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// spi_rx_1byte_data |
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// spi_rx_1byte_data_valid |
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// |
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reg [7:0] spi_rx_1byte_data = 0; |
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reg spi_rx_1byte_data_valid = 0; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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spi_rx_1byte_data <= 0; |
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spi_rx_1byte_data_valid <= 0; |
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end else begin |
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if (spi_cs_pin) begin |
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spi_rx_1byte_data <= 0; |
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spi_rx_1byte_data_valid <= 0; |
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end else begin |
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if (spi_clk_posedge_tri) begin |
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spi_rx_1byte_data[bit_cnt] <= spi_rx_pin; |
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end |
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if (spi_clk_negedge_tri && bit_cnt == 7) spi_rx_1byte_data_valid <= 1; |
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else spi_rx_1byte_data_valid <= 0; |
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end |
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end |
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end |
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/******************************************************************************* |
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* 缓存接收到的数据 * |
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*******************************************************************************/ |
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reg [7:0] spi_rx_data_cache [0:ADDRESS_WIDTH_BYTE_NUM+4-1] = 0; |
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reg [7:0] rx_byte_count = 0; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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rx_byte_count <= 0; |
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spi_rx_data_cache[0] <= 0; |
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spi_rx_data_cache[1] <= 0; |
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spi_rx_data_cache[2] <= 0; |
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spi_rx_data_cache[3] <= 0; |
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spi_rx_data_cache[4] <= 0; |
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spi_rx_data_cache[5] <= 0; |
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end else begin |
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if (spi_cs_pin) begin |
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// 失能状态 |
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rx_byte_count <= 0; |
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spi_rx_data_cache[0] <= 0; |
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spi_rx_data_cache[1] <= 0; |
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spi_rx_data_cache[2] <= 0; |
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spi_rx_data_cache[3] <= 0; |
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spi_rx_data_cache[4] <= 0; |
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spi_rx_data_cache[5] <= 0; |
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end else begin |
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// 选中状态 |
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if (spi_rx_1byte_data_valid) begin |
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rx_byte_count <= rx_byte_count + 1; |
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if (rx_byte_count < ADDRESS_WIDTH_BYTE_NUM + 4) begin |
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spi_rx_data_cache[rx_byte_count] <= spi_rx_1byte_data; |
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end |
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end |
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end |
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end |
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end |
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/******************************************************************************* |
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* 自动设置SPI需要发送的数据 spi_tx_1byte_data * |
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*******************************************************************************/ |
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always @(*) begin |
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case (spi_byte_cnt) |
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ADDRESS_WIDTH_BYTE_NUM + 0: spi_tx_1byte_data <= rd_data[7:0]; |
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ADDRESS_WIDTH_BYTE_NUM + 1: spi_tx_1byte_data <= rd_data[15:8]; |
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ADDRESS_WIDTH_BYTE_NUM + 2: spi_tx_1byte_data <= rd_data[23:16]; |
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ADDRESS_WIDTH_BYTE_NUM + 3: spi_tx_1byte_data <= rd_data[31:24]; |
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default: spi_tx_1byte_data <= 0; |
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endcase |
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end |
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/******************************************************************************* |
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* 自动设置addr数值 * |
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*******************************************************************************/ |
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always @(*) begin |
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case (ADDRESS_WIDTH_BYTE_NUM) |
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0: begin |
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addr[6:0] <= spi_rx_data_cache[0][6:0]; |
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end |
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1: begin |
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addr[7:0] <= spi_rx_data_cache[0][7:0]; |
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addr[14:8] <= spi_rx_data_cache[1][6:0]; |
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end |
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2: begin |
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addr[7:0] <= spi_rx_data_cache[0][7:0]; |
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addr[15:8] <= spi_rx_data_cache[1][7:0]; |
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addr[22:16] <= spi_rx_data_cache[2][6:0]; |
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end |
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3: begin |
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addr[7:0] <= spi_rx_data_cache[0][7:0]; |
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addr[15:8] <= spi_rx_data_cache[1][7:0]; |
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addr[23:16] <= spi_rx_data_cache[2][7:0]; |
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addr[30:24] <= spi_rx_data_cache[3][6:0]; |
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end |
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endcase |
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end |
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/******************************************************************************* |
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* wr_data * |
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*******************************************************************************/ |
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always @(*) begin |
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wr_data[7:0] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM]; |
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wr_data[15:8] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+1]; |
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wr_data[23:16] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+2]; |
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wr_data[31:24] <= spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM+3]; |
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end |
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/******************************************************************************* |
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* wr_en * |
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*******************************************************************************/ |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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wr_en <= 0; |
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end else begin |
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if (!spi_cs_pin && spi_clk_negedge_tri && spi_byte_cnt == ADDRESS_WIDTH_BYTE_NUM + 4) begin |
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wr_en <= 1; |
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end else begin |
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wr_en <= 0; |
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end |
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end |
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end |
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endmodule |
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@ -0,0 +1,208 @@ |
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module src_timecode_parser #( |
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parameter REG_START_ADD = 0 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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//regbus interface |
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output reg [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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inout wire [31:0] rd_data, //received serial data |
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// 输入 |
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input timecode_signal_in, |
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//输出 |
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output wire timecode_signal_orgin_output, //ttl原始数据 |
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output wire timecode_freq_trigger_signal |
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); |
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/******************************************************************************* |
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* 寄存器读写 * |
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*******************************************************************************/ |
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// |
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// @功能: |
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// 1. 采样TIMECODE信号 |
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// 2. 转发TIMECODE信号 |
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// 3. TIMECODE信号成功解析 |
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// 4. TIMECODE采样计数 |
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// |
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// @寄存器列表: |
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// 地址 读写 默认 描述 |
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// 0x00 wr 0x0 timecode bit周期 |
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// 0x01 r 0x0 flag bit[0]:timecode_ready_flag |
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// 0x02 r 0x0 timecode [31:0] |
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// 0x03 r 0x0 timecode [63:32] |
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// 0x04 r 0x0 timecode_ready_signal_pluse_width //识别到一帧timecode信号后，输出一个脉冲信号，用于同步其他模块 |
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parameter REG_TIMECODE_BIT_PERIOD_ADD = REG_START_ADD + 0; //timecode bit周期寄存器地址 |
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parameter ADD_NUM = 5; //寄存器数量 |
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parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 |
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reg [31:0] register[REG_START_ADD:REG_END_ADD]; |
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integer i; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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for (i = 0; i < ADD_NUM; i = i + 1) begin |
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register[i] <= 0; |
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end |
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end else begin |
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if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; |
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end |
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end |
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assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; |
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// 416us 500us 520us |
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// 边沿触发--> 采样偏移同步 |
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// |
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// 416us采用 160byte 采样到同步 |
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// 电平变化修正采样计数 |
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// |
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// 配置: |
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// 1. 制式 |
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// 2. |
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// 边沿信号捕获 |
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reg [160-1:0] tc_bit_2x; //timecode 每1/2bit |
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reg [79:0] tc_bit; //timecode 每1bit |
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reg sample_signal; //采样信号 |
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reg [31:0] sample_time_cnt; //采样计数 |
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wire sample_time_calibrate_signal; //采样信号修正器 |
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reg time_code_signal_edge; //timecode原始信号的边沿信号，即timecode上升沿或者下降沿时，置1 |
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assign timecode_signal_in_a = timecode_signal_in; // |
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reg timecode_signal_in_b; // |
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reg tc_sync_signal_edge; // timecode捕获到同步信号时，置1，此时可以解析timecode信号，并将其存放到寄存中 |
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/******************************************************************************* |
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* timecode边沿信号捕获 * |
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*******************************************************************************/ |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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timecode_signal_in_b <= 0; |
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end else begin |
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timecode_signal_in_b <= timecode_signal_in_a; |
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end |
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end |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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time_code_signal_edge <= 0; |
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end else begin |
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if (timecode_signal_in_a != timecode_signal_in_b) begin |
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time_code_signal_edge <= 1; |
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end else begin |
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time_code_signal_edge <= 0; |
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end |
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end |
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end |
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assign sample_time_calibrate_signal = time_code_signal_edge; |
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/******************************************************************************* |
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* BIT信号映射 * |
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*******************************************************************************/ |
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// |
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// 采样点 采样点 采样点 采样点 |
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// + + + + |
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// ___------------_______-------- |
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// 0 1 |
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// timecode的每个bit要通过两个点进行判断，所以需要2x的采样率 |
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// |
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always @(*) begin |
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for (i = 0; i < 79; i = i + 1) begin |
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tc_bit[i] = !tc_bit_2x[i*2] & tc_bit_2x[i*2+1]; |
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end |
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end |
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/******************************************************************************* |
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* 采样信号生成器 * |
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*******************************************************************************/ |
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// |
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// 1. 当捕获到timecode原始信号的边沿时，校准采样信号计数器 |
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// 2. 当采样信号计数器到达采样点时，输出采样信号 |
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// 3. 当采样信号计数器到达2倍采样点时，重置采样信号计数器 |
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// |
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assign timecode_sample_cnt_reset_signal = ( |
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sample_time_calibrate_signal|| |
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sample_time_cnt >= (register[REG_TIMECODE_BIT_PERIOD_ADD] << 1) |
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); |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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sample_time_cnt <= 0; |
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sample_signal <= 0; |
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end else begin |
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if (timecode_sample_cnt_reset_signal) begin |
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sample_time_cnt <= 0; |
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sample_signal <= 0; |
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end else if (sample_time_cnt == register[REG_TIMECODE_BIT_PERIOD_ADD]) begin |
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sample_time_cnt <= sample_time_cnt + 1; |
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sample_signal <= 1; |
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end else begin |
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sample_time_cnt <= sample_time_cnt + 1; |
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sample_signal <= 0; |
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end |
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end |
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end |
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// |
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// 根据sample_signal捕获timecode信号 |
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// |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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tc_bit_2x <= 0; |
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end else begin |
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if (sample_signal) begin |
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tc_bit_2x <= {tc_bit_2x[158:0], timecode_signal_in}; |
||||
|
end else begin |
||||
|
tc_bit_2x <= tc_bit_2x; |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
/******************************************************************************* |
||||
|
* tc_sync_signal_edge * |
||||
|
*******************************************************************************/ |
||||
|
// ___------------_______-------- |
||||
|
// 0 1 |
||||
|
// |
||||
|
// 捕获timecode同步信号 |
||||
|
// |
||||
|
// 同步信号 |
||||
|
// 0011_1111_11111_1101 |
||||
|
// 1111_0101__0101_0101__0101_0101__0101_1101 |
||||
|
// |
||||
|
reg [31:0] sync_code_pattern = 32'b1111_0101__0101_0101__0101_0101__0101_1101; |
||||
|
assign tc_sync_signal = (tc_bit == sync_code_pattern); |
||||
|
reg tc_sync_signal_b; |
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
tc_sync_signal_b <= 0; |
||||
|
end else begin |
||||
|
tc_sync_signal_b <= tc_sync_signal; |
||||
|
|
||||
|
if (tc_sync_signal & !tc_sync_signal_b) begin |
||||
|
tc_sync_signal_edge <= 1; |
||||
|
end else begin |
||||
|
tc_sync_signal_edge <= 0; |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
assign timecode_freq_trigger_signal = tc_sync_signal_edge; |
||||
|
|
||||
|
|
||||
|
|
||||
|
endmodule |
||||
@ -0,0 +1,45 @@ |
|||||
|
module zutils_edge_detecter ( |
||||
|
input clk, //clock input |
||||
|
input rst_n, //asynchronous reset input, low active |
||||
|
input wire signal_in |
||||
|
|
||||
|
); |
||||
|
|
||||
|
reg signal_in_last = 0; |
||||
|
assign now = signal_in; |
||||
|
assign last = signal_in_last; |
||||
|
|
||||
|
reg rsing_edge_signal; |
||||
|
reg falling_edge_signal; |
||||
|
reg edge_sginal; |
||||
|
|
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
signal_in_last <= 0; |
||||
|
end else begin |
||||
|
signal_in_last <= signal_in; |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
rsing_edge_signal <= 0; |
||||
|
falling_edge_signal <= 0; |
||||
|
edge_sginal <= 0; |
||||
|
end else begin |
||||
|
if (signal_in_last == 0 && signal_in == 1) begin |
||||
|
rsing_edge_signal <= 1; |
||||
|
falling_edge_signal <= 0; |
||||
|
edge_sginal <= 1; |
||||
|
end else if (signal_in_last == 1 && signal_in == 0) begin |
||||
|
rsing_edge_signal <= 0; |
||||
|
falling_edge_signal <= 1; |
||||
|
edge_sginal <= 1; |
||||
|
end else begin |
||||
|
rsing_edge_signal <= 0; |
||||
|
falling_edge_signal <= 0; |
||||
|
edge_sginal <= 0; |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
endmodule |
||||
@ -0,0 +1,29 @@ |
|||||
|
module zutils_pluse_generator ( |
||||
|
input clk, //clock input |
||||
|
input rst_n, //asynchronous reset input, low active |
||||
|
|
||||
|
input wire [31:0] pluse_width, |
||||
|
input wire trigger, |
||||
|
output reg pluse |
||||
|
); |
||||
|
|
||||
|
reg [31:0] counter = 0; |
||||
|
|
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
counter <= 0; |
||||
|
pluse <= 0; |
||||
|
end else begin |
||||
|
if (trigger) begin |
||||
|
counter <= pluse_width; |
||||
|
pluse <= 1; |
||||
|
end else begin |
||||
|
if (counter == 0) begin |
||||
|
pluse <= 0; |
||||
|
end else begin |
||||
|
counter <= counter - 1; |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
endmodule |
||||
@ -0,0 +1,31 @@ |
|||||
|
module zutils_register #( |
||||
|
parameter REG_START_ADD = 0, |
||||
|
parameter ADD_NUM = 10 |
||||
|
) ( |
||||
|
input clk, //clock input |
||||
|
input rst_n, //asynchronous reset input, low active |
||||
|
|
||||
|
//regbus interface |
||||
|
output reg [31:0] addr, |
||||
|
input [31:0] wr_data, |
||||
|
input wr_en, |
||||
|
|
||||
|
inout wire [31:0] rd_data //received serial data |
||||
|
); |
||||
|
|
||||
|
parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 |
||||
|
reg [31:0] data[REG_START_ADD:REG_END_ADD]; |
||||
|
integer i; |
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
for (i = 0; i < ADD_NUM; i = i + 1) begin |
||||
|
data[i] <= 0; |
||||
|
end |
||||
|
end else begin |
||||
|
if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) data[addr] <= wr_data; |
||||
|
end |
||||
|
end |
||||
|
assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr] : 31'bz; |
||||
|
|
||||
|
|
||||
|
endmodule |
||||
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