From c6028d9bfd8e39d45eca79c60d17255ebf36785c Mon Sep 17 00:00:00 2001 From: zhaohe Date: Mon, 8 Jan 2024 21:34:07 +0800 Subject: [PATCH] update --- led_test.pds | 56 +++++++++++++++++++++---------------------- source/src/top.v | 72 ++++++++++++++++++++++++++++++++++---------------------- 2 files changed, 72 insertions(+), 56 deletions(-) diff --git a/led_test.pds b/led_test.pds index 3fa527c..67915fd 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 21:14:56 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 21:31:11 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-08T21:14:35") + (_timespec "2024-01-08T21:28:52") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -128,17 +128,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-08T21:14:39") + (_timespec "2024-01-08T21:30:52") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-08T21:14:39") + (_timespec "2024-01-08T21:30:52") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-08T21:14:39") + (_timespec "2024-01-08T21:30:52") ) ) ) @@ -154,21 +154,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-01-08T21:14:41") + (_timespec "2024-01-08T21:30:55") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-01-08T21:14:41") + (_timespec "2024-01-08T21:30:55") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-01-08T21:14:41") + (_timespec "2024-01-08T21:30:55") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-08T21:14:41") + (_timespec "2024-01-08T21:30:55") ) ) ) @@ -189,21 +189,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-01-08T21:14:44") + (_timespec "2024-01-08T21:30:57") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-01-08T21:14:44") + (_timespec "2024-01-08T21:30:57") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-01-08T21:14:44") + (_timespec "2024-01-08T21:30:57") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-01-08T21:14:44") + (_timespec "2024-01-08T21:30:57") ) ) ) @@ -212,7 +212,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-08T21:14:44") + (_timespec "2024-01-08T21:30:57") ) ) ) @@ -226,33 +226,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-01-08T21:14:48") + (_timespec "2024-01-08T21:31:02") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-01-08T21:14:48") + (_timespec "2024-01-08T21:31:02") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-01-08T21:14:48") + (_timespec "2024-01-08T21:31:02") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-01-08T21:14:47") + (_timespec "2024-01-08T21:31:02") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-01-08T21:14:47") + (_timespec "2024-01-08T21:31:01") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-01-08T21:14:48") + (_timespec "2024-01-08T21:31:02") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-01-08T21:14:48") + (_timespec "2024-01-08T21:31:03") ) ) ) @@ -268,17 +268,17 @@ (_db_output (_file "report_timing/Top_rtp.adf" (_format adif) - (_timespec "2024-01-08T21:14:51") + (_timespec "2024-01-08T21:31:06") ) ) (_output (_file "report_timing/Top.rtr" (_format text) - (_timespec "2024-01-08T21:14:51") + (_timespec "2024-01-08T21:31:06") ) (_file "report_timing/rtr.db" (_format text) - (_timespec "2024-01-08T21:14:52") + (_timespec "2024-01-08T21:31:06") ) ) ) @@ -302,19 +302,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-01-08T21:14:56") + (_timespec "2024-01-08T21:31:10") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-01-08T21:14:56") + (_timespec "2024-01-08T21:31:10") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-01-08T21:14:56") + (_timespec "2024-01-08T21:31:10") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-01-08T21:14:56") + (_timespec "2024-01-08T21:31:11") ) ) ) diff --git a/source/src/top.v b/source/src/top.v index 058b2d4..42e9990 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -205,8 +205,24 @@ module Top ( * TEST_SPI_REG * *******************************************************************************/ zutils_register16 #( - .REG_START_ADD(`REG_ADD_OFF_FPGA_TEST) - ) core_board_debug_led_reg ( + .REG_START_ADD(`REG_ADD_OFF_FPGA_TEST), + .REG0_INIT(31'h0000_0000), + .REG1_INIT(31'h1111_1111), + .REG2_INIT(31'h2222_2222), + .REG3_INIT(31'h3333_3333), + .REG4_INIT(31'h4444_4444), + .REG5_INIT(31'h5555_5555), + .REG6_INIT(31'h6666_6666), + .REG7_INIT(31'h7777_7777), + .REG8_INIT(31'h8888_8888), + .REG9_INIT(31'h9999_9999), + .REGA_INIT(31'haaaa_aaaa), + .REGB_INIT(31'hbbbb_bbbb), + .REGC_INIT(31'hcccc_cccc), + .REGD_INIT(31'hdddd_dddd), + .REGE_INIT(31'heeee_eeee), + .REGF_INIT(31'hffff_ffff) + ) test_reg ( .clk(sys_clk), .rst_n(rst_n), .addr(reg_reader_bus_addr), @@ -299,38 +315,38 @@ module Top ( // ); -// rd_data_router rd_data_router_inst ( -// .addr(reg_reader_bus_addr), - -// .stm32_rd_data(stm32_rd_data), -// .fpga_test_rd_data(fpga_test_rd_data), -// .control_sensor_rd_data(control_sensor_rd_data), -// .ttlin1_rd_data(ttlin1_rd_data), -// .ttlin2_rd_data(ttlin2_rd_data), -// .ttlin3_rd_data(ttlin3_rd_data), -// .ttlin4_rd_data(ttlin4_rd_data), -// .timecode_in_rd_data(timecode_in_rd_data), -// .genlock_in_rd_data(genlock_in_rd_data), - -// .ttlout1_rd_data(ttlout1_rd_data), // ok -// .ttlout2_rd_data(ttlout2_rd_data), // ok -// .ttlout3_rd_data(ttlout3_rd_data), // ok -// .ttlout4_rd_data(ttlout4_rd_data), // ok - -// .timecode_out_rd_data(timecode_out_rd_data), -// .genlock_out_rd_data(genlock_out_rd_data), -// .stm32_if_rd_data(stm32_if_rd_data), -// .debuger_rd_data(debuger_rd_data), + // rd_data_router rd_data_router_inst ( + // .addr(reg_reader_bus_addr), -// .rd_data_out(reg_reader_bus_rd_data) -// ); - assign fpga_test_rd_data = reg_reader_bus_rd_data; + // .stm32_rd_data(stm32_rd_data), + // .fpga_test_rd_data(fpga_test_rd_data), + // .control_sensor_rd_data(control_sensor_rd_data), + // .ttlin1_rd_data(ttlin1_rd_data), + // .ttlin2_rd_data(ttlin2_rd_data), + // .ttlin3_rd_data(ttlin3_rd_data), + // .ttlin4_rd_data(ttlin4_rd_data), + // .timecode_in_rd_data(timecode_in_rd_data), + // .genlock_in_rd_data(genlock_in_rd_data), + + // .ttlout1_rd_data(ttlout1_rd_data), // ok + // .ttlout2_rd_data(ttlout2_rd_data), // ok + // .ttlout3_rd_data(ttlout3_rd_data), // ok + // .ttlout4_rd_data(ttlout4_rd_data), // ok + + // .timecode_out_rd_data(timecode_out_rd_data), + // .genlock_out_rd_data(genlock_out_rd_data), + // .stm32_if_rd_data(stm32_if_rd_data), + // .debuger_rd_data(debuger_rd_data), + + // .rd_data_out(reg_reader_bus_rd_data) + // ); + assign reg_reader_bus_rd_data[31:0] = fpga_test_rd_data[31:0]; assign debug_signal_output[0] = spi2_cs_pin; assign debug_signal_output[1] = spi2_clk_pin; assign debug_signal_output[2] = spi2_rx_pin; assign debug_signal_output[3] = spi2_tx_pin; - assign core_board_debug_led = 1; + assign core_board_debug_led = 1;