5 changed files with 333 additions and 27 deletions
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44led_test.pds
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40source/src/top.v
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200source/src/ttl_input.v
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46source/src/zutils/ztuils_sig_devide.v
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30source/src/zutils/zutils_signal_filter_advance.v
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// |
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// @功能: |
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// 1. 分频 |
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// 2. 滤波(add later) |
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// |
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module ttl_input #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000, |
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// parameter TEST = 0, |
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parameter ID = 1 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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//寄存器读写接口 |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output wire [31:0] rd_data, |
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|
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input ttlin1, |
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input ttlin2, |
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input ttlin3, |
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input ttlin4, |
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|
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//指示灯 |
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output ttlin1_state_led, |
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output ttlin2_state_led, |
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output ttlin3_state_led, |
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output ttlin4_state_led, |
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|
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//原始信号输入 |
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output ttlin1_ext, |
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output ttlin2_ext, |
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output ttlin3_ext, |
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output ttlin4_ext, |
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|
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//分频后的信号 |
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output ttlin1_divide, |
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output ttlin2_divide, |
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output ttlin3_divide, |
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output ttlin4_divide |
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|
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); |
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|
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reg [31:0] r0_ttlin_en; //信号源选择 0:off,1:bnc,2:headphone |
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reg [31:0] r1_ttlin1_devide_factor; // 分频因子 |
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reg [31:0] r2_ttlin2_devide_factor; // 分频因子 |
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reg [31:0] r3_ttlin3_devide_factor; // 分频因子 |
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reg [31:0] r4_ttlin4_devide_factor; // 分频因子 |
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reg [31:0] r5_ttlin1_filter_factor; // 滤波 |
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reg [31:0] r6_ttlin2_filter_factor; // 滤波 |
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reg [31:0] r7_ttlin3_filter_factor; // 滤波 |
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reg [31:0] r8_ttlin4_filter_factor; // 滤波 |
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|
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|
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wire [31:0] reg_wr_index; |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.addr(addr), |
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.wr_data(wr_data), |
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.wr_en(wr_en), |
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.rd_data(rd_data), |
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|
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.reg0(r0_ttlin_en), |
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.reg1(r1_ttlin1_devide_factor), |
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.reg2(r2_ttlin2_devide_factor), |
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.reg3(r3_ttlin3_devide_factor), |
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.reg4(r4_ttlin4_devide_factor), |
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|
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r0_ttlin_en <= 0; |
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r1_ttlin1_devide_factor <= 0; |
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r2_ttlin2_devide_factor <= 0; |
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r3_ttlin3_devide_factor <= 0; |
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r4_ttlin4_devide_factor <= 0; |
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r5_ttlin1_filter_factor <= 0; |
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r6_ttlin2_filter_factor <= 0; |
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r7_ttlin3_filter_factor <= 0; |
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r8_ttlin4_filter_factor <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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0: r0_ttlin_en <= wr_data; |
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1: r1_ttlin1_devide_factor <= wr_data; |
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2: r2_ttlin2_devide_factor <= wr_data; |
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3: r3_ttlin3_devide_factor <= wr_data; |
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4: r4_ttlin4_devide_factor <= wr_data; |
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5: r5_ttlin1_filter_factor <= wr_data; |
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6: r6_ttlin2_filter_factor <= wr_data; |
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7: r7_ttlin3_filter_factor <= wr_data; |
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8: r8_ttlin4_filter_factor <= wr_data; |
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|
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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|
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// 使能 --> 滤波 --> 分频 --> 输出 |
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|
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// 使能 |
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assign ttlin1_sig = r0_ttlin_en[0] & ttlin1; |
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assign ttlin2_sig = r0_ttlin_en[1] & ttlin2; |
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assign ttlin3_sig = r0_ttlin_en[2] & ttlin3; |
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assign ttlin4_sig = r0_ttlin_en[3] & ttlin4; |
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|
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// 滤波 |
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wire ttlin1_sig_af_filter; |
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wire ttlin2_sig_af_filter; |
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wire ttlin3_sig_af_filter; |
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wire ttlin4_sig_af_filter; |
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|
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zutils_signal_filter_advance filter1 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.filter_delay_count(r5_ttlin1_filter_factor), |
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.in(ttlin1_sig), |
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.out(ttlin1_sig_af_filter) |
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); |
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zutils_signal_filter_advance filter2 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.filter_delay_count(r6_ttlin2_filter_factor), |
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.in(ttlin2_sig), |
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.out(ttlin2_sig_af_filter) |
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); |
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zutils_signal_filter_advance filter3 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.filter_delay_count(r7_ttlin3_filter_factor), |
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.in(ttlin3_sig), |
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.out(ttlin3_sig_af_filter) |
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); |
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zutils_signal_filter_advance filter4 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.filter_delay_count(r8_ttlin4_filter_factor), |
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.in(ttlin4_sig), |
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.out(ttlin4_sig_af_filter) |
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); |
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|
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//分频 |
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wire ttlin1_sig_af_devide; |
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wire ttlin2_sig_af_devide; |
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wire ttlin3_sig_af_devide; |
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wire ttlin4_sig_af_devide; |
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|
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ztuils_sig_devide sig_devide1 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in(ttlin1_sig_af_filter), |
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.out(ttlin1_sig_af_devide) |
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); |
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ztuils_sig_devide sig_devide2 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in(ttlin2_sig_af_filter), |
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.out(ttlin2_sig_af_devide) |
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); |
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ztuils_sig_devide sig_devide3 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in(ttlin3_sig_af_filter), |
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.out(ttlin3_sig_af_devide) |
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); |
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ztuils_sig_devide sig_devide4 ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in(ttlin4_sig_af_filter), |
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.out(ttlin4_sig_af_devide) |
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); |
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assign ttlin1_state_led = 1; |
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assign ttlin2_state_led = 1; |
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assign ttlin3_state_led = 1; |
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assign ttlin4_state_led = 1; |
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|
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//原始信号输入 |
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assign ttlin1_ext = ttlin1_sig_af_filter; |
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assign ttlin2_ext = ttlin2_sig_af_filter; |
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assign ttlin3_ext = ttlin3_sig_af_filter; |
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assign ttlin4_ext = ttlin4_sig_af_filter; |
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|
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//分频后的信号 |
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assign ttlin1_divide = ttlin1_sig_af_devide; |
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assign ttlin2_divide = ttlin2_sig_af_devide; |
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assign ttlin3_divide = ttlin3_sig_af_devide; |
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assign ttlin4_divide = ttlin4_sig_af_devide; |
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|
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|
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endmodule |
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@ -0,0 +1,46 @@ |
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// |
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// @功能: |
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// 1. 分频 |
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// |
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module ztuils_sig_devide ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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//寄存器读写接口 |
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input [31:0] devide, |
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|
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input in, |
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output reg out |
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); |
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|
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wire in_rising_adge; |
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// 边沿检测 |
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zutils_edge_detecter _signal_in ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(in), |
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.in_signal_rising_edge(in_rising_adge) |
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); |
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|
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|
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|
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reg [31:0] ttl_in_cnt; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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ttl_in_cnt <= 0; |
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out <= 0; |
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end else begin |
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if (in_rising_adge) begin |
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if (ttl_in_cnt >= devide) begin |
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ttl_in_cnt <= 0; |
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out <= 1; |
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end else begin |
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ttl_in_cnt <= ttl_in_cnt + 1; |
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end |
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end else begin |
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out <= 0; |
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end |
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end |
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end |
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|
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endmodule |
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@ -0,0 +1,30 @@ |
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module zutils_signal_filter_advance #( |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input [31:0] filter_delay_count, |
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input wire in, |
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output reg out |
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); |
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// initial out = 0; |
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reg [31:0] counter = 0; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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counter <= 0; |
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out <= in; |
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|
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end else begin |
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if (out != in) begin |
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if (counter == filter_delay_count) begin |
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counter <= 0; |
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out <= in; |
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end else begin |
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counter <= counter + 1; |
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end |
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end else begin |
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counter <= 0; |
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end |
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end |
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end |
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|
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endmodule |
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