add ttl_input

led_test.pds

@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Jan 12 13:47:32 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Jan 12 14:25:50 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -19,7 +19,7 @@
             (_input
                 (_file "source/src/top.v" + "Top:"
                     (_format verilog)
-                    (_timespec "2024-01-12T13:47:07")
+                    (_timespec "2024-01-12T14:24:24")
                 )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
@@ -153,6 +153,18 @@
                     (_format verilog)
                     (_timespec "2024-01-12T13:46:21")
                 )
+                (_file "source/src/zutils/ztuils_sig_devide.v"
+                    (_format verilog)
+                    (_timespec "2024-01-12T14:14:11")
+                )
+                (_file "source/src/ttl_input.v"
+                    (_format verilog)
+                    (_timespec "2024-01-12T14:20:08")
+                )
+                (_file "source/src/zutils/zutils_signal_filter_advance.v"
+                    (_format verilog)
+                    (_timespec "2024-01-12T14:02:02")
+                )
             )
         )
         (_widget wgt_my_ips_src
@@ -223,17 +235,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-01-12T13:47:11")
+                    (_timespec "2024-01-12T14:25:50")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-01-12T13:47:10")
+                    (_timespec "2024-01-12T14:25:48")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-01-12T13:47:12")
+                    (_timespec "2024-01-12T14:25:50")
                 )
             )
         )
@@ -243,29 +255,9 @@
     )
     (_task tsk_synthesis
         (_command cmd_synthesize
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_option ads (_switch ON))
             (_option selected_syn_tool_opt (_integer 2))
-            (_db_output
-                (_file "synthesize/Top_syn.adf"
-                    (_format adif)
-                    (_timespec "2024-01-12T13:47:30")
-                )
-            )
-            (_output
-                (_file "synthesize/Top_syn.vm"
-                    (_format structural_verilog)
-                    (_timespec "2024-01-12T13:47:31")
-                )
-                (_file "synthesize/Top.snr"
-                    (_format text)
-                    (_timespec "2024-01-12T13:47:32")
-                )
-                (_file "synthesize/snr.db"
-                    (_format text)
-                    (_timespec "2024-01-12T13:47:32")
-                )
-            )
         )
         (_widget wgt_tech_view
             (_attribute _click_to_run (_switch ON))

source/src/top.v

@@ -343,6 +343,42 @@ module Top (
       .timecode_bnc_in_state_led(timecode_bnc_in_state_led)
   );
 
+  ttl_input #(
+      .REG_START_ADD (REG_ADD_OFF_TTLIN1),
+      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
+  ) ttl_inputr_ins (
+      .clk  (sys_clk),
+      .rst_n(sys_rst_n),
+
+      .addr(reg_reader_bus_addr),
+      .wr_data(reg_reader_bus_wr_data),
+      .wr_en(reg_reader_bus_wr_en),
+      .rd_data(ttlin1_rd_data),
+
+    .ttlin1(sync_ttl_in1),
+    .ttlin2(sync_ttl_in2),
+    .ttlin3(sync_ttl_in3),
+    .ttlin4(sync_ttl_in4),
+
+    //指示灯 
+    .ttlin1_state_led(sync_ttl_in1_state_led),
+    .ttlin2_state_led(sync_ttl_in2_state_led),
+    .ttlin3_state_led(sync_ttl_in3_state_led),
+    .ttlin4_state_led(sync_ttl_in4_state_led),
+
+    //原始信号
+    .ttlin1_ext(ISIG_ttlin1_module_ext),
+    .ttlin2_ext(ISIG_ttlin2_module_ext),
+    .ttlin3_ext(ISIG_ttlin3_module_ext),
+    .ttlin4_ext(ISIG_ttlin4_module_ext),
+
+    //分频后的信号
+    .ttlin1_divide(ISIG_ttlin1_module_divide),
+    .ttlin2_divide(ISIG_ttlin2_module_divide),
+    .ttlin3_divide(ISIG_ttlin3_module_divide),
+    .ttlin4_divide(ISIG_ttlin4_module_divide)
+  );
+
   /*******************************************************************************
      *                         ISIG_internal_100hz信号生成                         *
      *******************************************************************************/
@@ -355,6 +391,8 @@ module Top (
       .output_signal(ISIG_internal_100hz)
   );
 
+  
+
 
   // ===========================================================================================================
   //  输出组件
@@ -582,6 +620,6 @@ module Top (
   assign core_board_debug_led = 1;
   assign genlock_in_state_led = 1;
 
-
+  assign stm32if_start_signal_out = ISIG_internal_en_flag;
 
 endmodule

source/src/ttl_input.v

@@ -0,0 +1,200 @@
+//
+//  @功能:
+//          1. 分频
+//          2. 滤波(add later)
+//    
+module ttl_input #(
+    parameter REG_START_ADD = 0,
+    parameter SYS_CLOCK_FREQ = 10000000,
+    // parameter TEST = 0,
+    parameter ID = 1
+) (
+    input clk,   //clock input
+    input rst_n, //asynchronous reset input, low active
+
+    //寄存器读写接口    
+    input       [31:0] addr,
+    input       [31:0] wr_data,
+    input              wr_en,
+    output wire [31:0] rd_data,
+
+    input ttlin1,
+    input ttlin2,
+    input ttlin3,
+    input ttlin4,
+
+    //指示灯 
+    output ttlin1_state_led,
+    output ttlin2_state_led,
+    output ttlin3_state_led,
+    output ttlin4_state_led,
+
+    //原始信号输入
+    output ttlin1_ext,
+    output ttlin2_ext,
+    output ttlin3_ext,
+    output ttlin4_ext,
+
+    //分频后的信号
+    output ttlin1_divide,
+    output ttlin2_divide,
+    output ttlin3_divide,
+    output ttlin4_divide
+
+);
+
+  reg  [31:0] r0_ttlin_en;  //信号源选择 0:off,1:bnc,2:headphone
+  reg  [31:0] r1_ttlin1_devide_factor;  // 分频因子
+  reg  [31:0] r2_ttlin2_devide_factor;  // 分频因子
+  reg  [31:0] r3_ttlin3_devide_factor;  // 分频因子
+  reg  [31:0] r4_ttlin4_devide_factor;  // 分频因子
+  reg  [31:0] r5_ttlin1_filter_factor;  // 滤波
+  reg  [31:0] r6_ttlin2_filter_factor;  // 滤波
+  reg  [31:0] r7_ttlin3_filter_factor;  // 滤波
+  reg  [31:0] r8_ttlin4_filter_factor;  // 滤波
+
+
+  wire [31:0] reg_wr_index;
+  zutils_register_advanced #(
+      .REG_START_ADD(REG_START_ADD)
+  ) _register (
+      .clk(clk),
+      .rst_n(rst_n),
+      .addr(addr),
+      .wr_data(wr_data),
+      .wr_en(wr_en),
+      .rd_data(rd_data),
+
+      .reg0(r0_ttlin_en),
+      .reg1(r1_ttlin1_devide_factor),
+      .reg2(r2_ttlin2_devide_factor),
+      .reg3(r3_ttlin3_devide_factor),
+      .reg4(r4_ttlin4_devide_factor),
+
+      .reg_wr_sig(reg_wr_sig),
+      .reg_index (reg_wr_index)
+  );
+
+  always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      r0_ttlin_en <= 0;
+      r1_ttlin1_devide_factor <= 0;
+      r2_ttlin2_devide_factor <= 0;
+      r3_ttlin3_devide_factor <= 0;
+      r4_ttlin4_devide_factor <= 0;
+      r5_ttlin1_filter_factor <= 0;
+      r6_ttlin2_filter_factor <= 0;
+      r7_ttlin3_filter_factor <= 0;
+      r8_ttlin4_filter_factor <= 0;
+    end else begin
+      if (reg_wr_sig) begin
+        case (reg_wr_index)
+          0: r0_ttlin_en <= wr_data;
+          1: r1_ttlin1_devide_factor <= wr_data;
+          2: r2_ttlin2_devide_factor <= wr_data;
+          3: r3_ttlin3_devide_factor <= wr_data;
+          4: r4_ttlin4_devide_factor <= wr_data;
+          5: r5_ttlin1_filter_factor <= wr_data;
+          6: r6_ttlin2_filter_factor <= wr_data;
+          7: r7_ttlin3_filter_factor <= wr_data;
+          8: r8_ttlin4_filter_factor <= wr_data;
+
+          default: begin
+          end
+        endcase
+      end
+    end
+  end
+
+  //   使能 --> 滤波 --> 分频 --> 输出
+
+  // 使能
+  assign ttlin1_sig = r0_ttlin_en[0] & ttlin1;
+  assign ttlin2_sig = r0_ttlin_en[1] & ttlin2;
+  assign ttlin3_sig = r0_ttlin_en[2] & ttlin3;
+  assign ttlin4_sig = r0_ttlin_en[3] & ttlin4;
+
+  // 滤波
+  wire ttlin1_sig_af_filter;
+  wire ttlin2_sig_af_filter;
+  wire ttlin3_sig_af_filter;
+  wire ttlin4_sig_af_filter;
+
+  zutils_signal_filter_advance filter1 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .filter_delay_count(r5_ttlin1_filter_factor),
+      .in(ttlin1_sig),
+      .out(ttlin1_sig_af_filter)
+  );
+  zutils_signal_filter_advance filter2 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .filter_delay_count(r6_ttlin2_filter_factor),
+      .in(ttlin2_sig),
+      .out(ttlin2_sig_af_filter)
+  );
+  zutils_signal_filter_advance filter3 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .filter_delay_count(r7_ttlin3_filter_factor),
+      .in(ttlin3_sig),
+      .out(ttlin3_sig_af_filter)
+  );
+  zutils_signal_filter_advance filter4 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .filter_delay_count(r8_ttlin4_filter_factor),
+      .in(ttlin4_sig),
+      .out(ttlin4_sig_af_filter)
+  );
+
+  //分频
+  wire ttlin1_sig_af_devide;
+  wire ttlin2_sig_af_devide;
+  wire ttlin3_sig_af_devide;
+  wire ttlin4_sig_af_devide;
+
+  ztuils_sig_devide sig_devide1 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .in(ttlin1_sig_af_filter),
+      .out(ttlin1_sig_af_devide)
+  );
+  ztuils_sig_devide sig_devide2 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .in(ttlin2_sig_af_filter),
+      .out(ttlin2_sig_af_devide)
+  );
+  ztuils_sig_devide sig_devide3 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .in(ttlin3_sig_af_filter),
+      .out(ttlin3_sig_af_devide)
+  );
+  ztuils_sig_devide sig_devide4 (
+      .clk(clk),
+      .rst_n(rst_n),
+      .in(ttlin4_sig_af_filter),
+      .out(ttlin4_sig_af_devide)
+  );
+  assign ttlin1_state_led = 1;
+  assign ttlin2_state_led = 1;
+  assign ttlin3_state_led = 1;
+  assign ttlin4_state_led = 1;
+
+  //原始信号输入
+  assign ttlin1_ext = ttlin1_sig_af_filter;
+  assign ttlin2_ext = ttlin2_sig_af_filter;
+  assign ttlin3_ext = ttlin3_sig_af_filter;
+  assign ttlin4_ext = ttlin4_sig_af_filter;
+
+  //分频后的信号
+  assign ttlin1_divide = ttlin1_sig_af_devide;
+  assign ttlin2_divide = ttlin2_sig_af_devide;
+  assign ttlin3_divide = ttlin3_sig_af_devide;
+  assign ttlin4_divide = ttlin4_sig_af_devide;
+
+
+endmodule

source/src/zutils/ztuils_sig_devide.v

@@ -0,0 +1,46 @@
+//
+//  @功能:
+//          1. 分频
+//    
+module ztuils_sig_devide (
+    input clk,   //clock input
+    input rst_n, //asynchronous reset input, low active
+
+    //寄存器读写接口    
+    input [31:0] devide,
+
+    input in,
+    output reg out
+);
+
+  wire in_rising_adge;
+  // 边沿检测
+  zutils_edge_detecter _signal_in (
+      .clk(clk),
+      .rst_n(rst_n),
+      .in_signal(in),
+      .in_signal_rising_edge(in_rising_adge)
+  );
+
+
+
+  reg [31:0] ttl_in_cnt;
+  always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      ttl_in_cnt <= 0;
+      out <= 0;
+    end else begin
+      if (in_rising_adge) begin
+        if (ttl_in_cnt >= devide) begin
+          ttl_in_cnt <= 0;
+          out <= 1;
+        end else begin
+          ttl_in_cnt <= ttl_in_cnt + 1;
+        end
+      end else begin
+        out <= 0;
+      end
+    end
+  end
+
+endmodule

source/src/zutils/zutils_signal_filter_advance.v

@@ -0,0 +1,30 @@
+module zutils_signal_filter_advance #(
+) (
+    input              clk,                 //clock input
+    input              rst_n,               //asynchronous reset input, low active
+    input       [31:0] filter_delay_count,
+    input  wire        in,
+    output reg         out
+);
+  // initial out = 0;
+  reg [31:0] counter = 0;
+  always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      counter <= 0;
+      out <= in;
+
+    end else begin
+      if (out != in) begin
+        if (counter == filter_delay_count) begin
+          counter <= 0;
+          out <= in;
+        end else begin
+          counter <= counter + 1;
+        end
+      end else begin
+        counter <= 0;
+      end
+    end
+  end
+
+endmodule