update

led_test.pds

@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Jan  7 18:36:45 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Jan  7 19:04:57 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -47,7 +47,7 @@
                 )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
-                    (_timespec "2024-01-07T18:20:46")
+                    (_timespec "2024-01-07T18:54:33")
                 )
                 (_file "source/src/src_ttl_parser.v"
                     (_format verilog)
@@ -83,7 +83,7 @@
                 )
                 (_file "source/src/zutils/zutils_signal_filter.v"
                     (_format verilog)
-                    (_timespec "2024-01-07T13:48:54")
+                    (_timespec "2024-01-07T18:57:38")
                 )
                 (_file "source/src/zutils/zutils_clk_parser.v"
                     (_format verilog)
@@ -129,7 +129,7 @@
                 )
                 (_file "source/test/test_top.v" + "test_top:"
                     (_format verilog)
-                    (_timespec "2024-01-07T18:35:46")
+                    (_timespec "2024-01-07T19:04:55")
                 )
                 (_file "source/test/test_uart_reg_reader.v"
                     (_format verilog)
@@ -144,21 +144,15 @@
     )
     (_task tsk_compile
         (_command cmd_compile
-            (_gci_state (_integer 2))
-            (_db_output
-                (_file "compile/Top_comp.adf"
-                    (_format adif)
-                    (_timespec "2024-01-07T18:36:45")
-                )
-            )
+            (_gci_state (_integer 1))
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-01-07T18:36:44")
+                    (_timespec "2024-01-07T18:57:21")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-01-07T18:36:45")
+                    (_timespec "2024-01-07T18:57:21")
                 )
             )
         )

source/src/spi_reg_reader.v

@@ -23,7 +23,7 @@ module spi_reg_reader (
   parameter ADDRESS_WIDTH_BYTE_NUM = 2;
 
   zutils_signal_filter #(
-      .FILTER_COUNT(2)
+      .FILTER_COUNT(1)
   ) cs_filter (
       .clk(clk),
       .rst_n(rst_n),
@@ -32,7 +32,7 @@ module spi_reg_reader (
   );
 
   zutils_signal_filter #(
-      .FILTER_COUNT(2)
+      .FILTER_COUNT(1)
   ) clk_filter (
       .clk(clk),
       .rst_n(rst_n),
@@ -41,7 +41,7 @@ module spi_reg_reader (
   );
 
   zutils_signal_filter #(
-      .FILTER_COUNT(2)
+      .FILTER_COUNT(1)
   ) spi_rx_filter (
       .clk(clk),
       .rst_n(rst_n),

source/src/zutils/zutils_signal_filter.v

@@ -10,24 +10,20 @@ module zutils_signal_filter #(
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       counter <= 0;
+      out <= in;
+
     end else begin
       if (out != in) begin
-        counter <= counter + 1;
+        if (counter == FILTER_COUNT) begin
+          counter <= 0;
+          out <= in;
+        end else begin
+          counter <= counter + 1;
+        end
       end else begin
         counter <= 0;
       end
     end
   end
 
-  always @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      out <= in;
-    end else begin
-      if (counter == FILTER_COUNT) begin
-        out <= in;
-      end else begin
-        out <= out;
-      end
-    end
-  end
 endmodule

source/test/test_top.v

@@ -18,22 +18,21 @@ module test_top;
 
 
   task spi_write_reg;
-
     input [15:0] addr;
     input [31:0] data;
     integer i;
     begin
       addr[15] = 1;
       spi1_cs_pin = 0;
-      #10;  // 100ns
+      #30;  // 100ns
 
       for (i = 0; i < 48; i = i + 1) begin
         spi1_clk_pin = 0;
         if (i <= 15) spi1_tx_pin = addr[i];
         else spi1_tx_pin = data[i-16];
-        #10;
+        #30;
         spi1_clk_pin = 1;
-        #10;
+        #30;
       end
       spi1_clk_pin = 0;
       #10;
@@ -42,10 +41,8 @@ module test_top;
       #20;
       spi1_cs_pin = 1;
       spi1_tx_pin = 1;
-      #100;
-
+      #300;
     end
-
   endtask
 
 
@@ -73,14 +70,14 @@ module test_top;
 
     #100;
     spi_write_reg(16'h0020, 32'h00000001);
-    spi_write_reg(16'h0021, 32'h00000020);
-    spi_write_reg(16'h0022, 32'h00000300);
-    spi_write_reg(16'h0023, 32'h00004000);
-    spi_write_reg(16'h0024, 32'h00050000);
-    spi_write_reg(16'h0025, 32'h00600000);
-    spi_write_reg(16'h0026, 32'h07000000);
-    spi_write_reg(16'h0027, 32'h80000000);
+    spi_write_reg(16'h0021, 32'h00000010);
+    spi_write_reg(16'h0022, 32'h00000100);
+    spi_write_reg(16'h0023, 32'h00001000);
 
+    spi_write_reg(16'h0020, 32'h00000002);
+    spi_write_reg(16'h0021, 32'h00000020);
+    spi_write_reg(16'h0022, 32'h00000200);
+    spi_write_reg(16'h0023, 32'h00002000);
   end
   always #1 sys_clk = ~sys_clk;  // 50MHZ时钟
 endmodule