zhaohe
/
fpga_led_test
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

update

master
zhaohe 2 years ago
parent
12d4a4834b
commit
e80472f44e
3 changed files with 152 additions and 129 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Unified View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 58
      led_test.pds
  2. 39
      source/src/rd_data_router.v
  3. 68
      source/src/top.v

58
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan 8 18:12:27 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan 8 18:56:57 2024")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -19,7 +19,7 @@
(_input (_input
(_file "source/src/top.v" + "Top:" (_file "source/src/top.v" + "Top:"
(_format verilog) (_format verilog)
(_timespec "2024-01-08T18:10:14")
(_timespec "2024-01-08T18:55:46")
) )
(_file "source/src/spi_reg_reader.v" (_file "source/src/spi_reg_reader.v"
(_format verilog) (_format verilog)
@ -67,7 +67,7 @@
) )
(_file "source/src/rd_data_router.v" (_file "source/src/rd_data_router.v"
(_format verilog) (_format verilog)
(_timespec "2024-01-08T17:44:45")
(_timespec "2024-01-08T18:48:27")
) )
) )
) )
@ -128,17 +128,17 @@
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2024-01-08T18:10:54")
(_timespec "2024-01-08T18:56:31")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2024-01-08T18:10:54")
(_timespec "2024-01-08T18:56:31")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2024-01-08T18:10:54")
(_timespec "2024-01-08T18:56:31")
) )
) )
) )
@ -154,21 +154,21 @@
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2024-01-08T18:10:57")
(_timespec "2024-01-08T18:56:35")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2024-01-08T18:10:57")
(_timespec "2024-01-08T18:56:35")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2024-01-08T18:10:58")
(_timespec "2024-01-08T18:56:35")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2024-01-08T18:10:58")
(_timespec "2024-01-08T18:56:36")
) )
) )
) )
@ -189,21 +189,21 @@
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2024-01-08T18:11:00")
(_timespec "2024-01-08T18:56:38")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:00")
(_timespec "2024-01-08T18:56:38")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:00")
(_timespec "2024-01-08T18:56:38")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:00")
(_timespec "2024-01-08T18:56:38")
) )
) )
) )
@ -212,7 +212,7 @@
(_input (_input
(_file "device_map/led_test.pcf" (_file "device_map/led_test.pcf"
(_format pcf) (_format pcf)
(_timespec "2024-01-08T18:11:00")
(_timespec "2024-01-08T18:56:38")
) )
) )
) )
@ -226,33 +226,33 @@
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2024-01-08T18:11:08")
(_timespec "2024-01-08T18:56:46")
) )
) )
(_output (_output
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:08")
(_timespec "2024-01-08T18:56:46")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:08")
(_timespec "2024-01-08T18:56:46")
) )
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:08")
(_timespec "2024-01-08T18:56:46")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2024-01-08T18:11:05")
(_timespec "2024-01-08T18:56:44")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:08")
(_timespec "2024-01-08T18:56:46")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:08")
(_timespec "2024-01-08T18:56:47")
) )
) )
) )
@ -268,17 +268,17 @@
(_db_output (_db_output
(_file "report_timing/Top_rtp.adf" (_file "report_timing/Top_rtp.adf"
(_format adif) (_format adif)
(_timespec "2024-01-08T18:11:11")
(_timespec "2024-01-08T18:56:51")
) )
) )
(_output (_output
(_file "report_timing/Top.rtr" (_file "report_timing/Top.rtr"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:11")
(_timespec "2024-01-08T18:56:51")
) )
(_file "report_timing/rtr.db" (_file "report_timing/rtr.db"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:12")
(_timespec "2024-01-08T18:56:51")
) )
) )
) )
@ -302,19 +302,19 @@
(_output (_output
(_file "generate_bitstream/Top.sbit" (_file "generate_bitstream/Top.sbit"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:17")
(_timespec "2024-01-08T18:56:56")
) )
(_file "generate_bitstream/Top.smsk" (_file "generate_bitstream/Top.smsk"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:17")
(_timespec "2024-01-08T18:56:56")
) )
(_file "generate_bitstream/Top.bgr" (_file "generate_bitstream/Top.bgr"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:17")
(_timespec "2024-01-08T18:56:56")
) )
(_file "generate_bitstream/bgr.db" (_file "generate_bitstream/bgr.db"
(_format text) (_format text)
(_timespec "2024-01-08T18:11:17")
(_timespec "2024-01-08T18:56:57")
) )
) )
) )

39
source/src/rd_data_router.v
View File

@ -28,26 +28,29 @@ module rd_data_router (
); );
initial rd_data_out = 0; initial rd_data_out = 0;
// wire [31:0] addr_8 = addr >> 8;
wire [31:0] addr_group;
assign addr_group = addr & 31'hFFFF_FFF0;
always @(*) begin always @(*) begin
case (addr >> 8)
`REG_ADD_OFF_STM32 >> 8: rd_data_out = stm32_rd_data;
`REG_ADD_OFF_FPGA_TEST >> 8: rd_data_out = fpga_test_rd_data;
`REG_ADD_OFF_CONTROL_SENSOR >> 8: rd_data_out = control_sensor_rd_data;
`REG_ADD_OFF_TTLIN1 >> 8: rd_data_out = ttlin1_rd_data;
`REG_ADD_OFF_TTLIN2 >> 8: rd_data_out = ttlin2_rd_data;
`REG_ADD_OFF_TTLIN3 >> 8: rd_data_out = ttlin3_rd_data;
`REG_ADD_OFF_TTLIN4 >> 8: rd_data_out = ttlin4_rd_data;
`REG_ADD_OFF_TIMECODE_IN >> 8: rd_data_out = timecode_in_rd_data;
`REG_ADD_OFF_GENLOCK_IN >> 8: rd_data_out = genlock_in_rd_data;
`REG_ADD_OFF_TTLOUT1 >> 8: rd_data_out = ttlout1_rd_data;
`REG_ADD_OFF_TTLOUT2 >> 8: rd_data_out = ttlout2_rd_data;
`REG_ADD_OFF_TTLOUT3 >> 8: rd_data_out = ttlout3_rd_data;
`REG_ADD_OFF_TTLOUT4 >> 8: rd_data_out = ttlout4_rd_data;
`REG_ADD_OFF_TIMECODE_OUT >> 8: rd_data_out = timecode_out_rd_data;
`REG_ADD_OFF_GENLOCK_OUT >> 8: rd_data_out = genlock_out_rd_data;
`REG_ADD_OFF_STM32_IF >> 8: rd_data_out = stm32_if_rd_data;
`REG_ADD_OFF_DEBUGER >> 8: rd_data_out = debuger_rd_data;
case (addr_group)
(`REG_ADD_OFF_STM32): rd_data_out = stm32_rd_data;
(`REG_ADD_OFF_FPGA_TEST): rd_data_out = fpga_test_rd_data;
(`REG_ADD_OFF_CONTROL_SENSOR): rd_data_out = control_sensor_rd_data;
(`REG_ADD_OFF_TTLIN1): rd_data_out = ttlin1_rd_data;
(`REG_ADD_OFF_TTLIN2): rd_data_out = ttlin2_rd_data;
(`REG_ADD_OFF_TTLIN3): rd_data_out = ttlin3_rd_data;
(`REG_ADD_OFF_TTLIN4): rd_data_out = ttlin4_rd_data;
(`REG_ADD_OFF_TIMECODE_IN): rd_data_out = timecode_in_rd_data;
(`REG_ADD_OFF_GENLOCK_IN): rd_data_out = genlock_in_rd_data;
(`REG_ADD_OFF_TTLOUT1): rd_data_out = ttlout1_rd_data;
(`REG_ADD_OFF_TTLOUT2): rd_data_out = ttlout2_rd_data;
(`REG_ADD_OFF_TTLOUT3): rd_data_out = ttlout3_rd_data;
(`REG_ADD_OFF_TTLOUT4): rd_data_out = ttlout4_rd_data;
(`REG_ADD_OFF_TIMECODE_OUT): rd_data_out = timecode_out_rd_data;
(`REG_ADD_OFF_GENLOCK_OUT): rd_data_out = genlock_out_rd_data;
(`REG_ADD_OFF_STM32_IF): rd_data_out = stm32_if_rd_data;
(`REG_ADD_OFF_DEBUGER): rd_data_out = debuger_rd_data;
default: rd_data_out = 0; default: rd_data_out = 0;
endcase endcase
end end

68
source/src/top.v
View File

@ -179,44 +179,40 @@ module Top (
.spi_tx_pin(spi2_tx_pin) .spi_tx_pin(spi2_tx_pin)
); );
wire [31:0] stm32_rd_data;
wire [31:0] fpga_test_rd_data;
wire [31:0] control_sensor_rd_data;
wire [31:0] ttlin1_rd_data;
wire [31:0] ttlin2_rd_data;
wire [31:0] ttlin3_rd_data;
wire [31:0] ttlin4_rd_data;
wire [31:0] timecode_in_rd_data;
wire [31:0] genlock_in_rd_data;
wire [31:0] ttlout1_rd_data;
wire [31:0] ttlout2_rd_data;
wire [31:0] ttlout3_rd_data;
wire [31:0] ttlout4_rd_data;
wire [31:0] timecode_out_rd_data;
wire [31:0] genlock_out_rd_data;
wire [31:0] stm32_if_rd_data;
wire [31:0] debuger_rd_data;
// rd_data_router rd_data_router_inst (
// .addr(reg_reader_bus_addr),
// .stm32_rd_data(0),
// .fpga_test_rd_data(fpga_test_rd_data),
// .control_sensor_rd_data(control_sensor_rd_data),
// .ttlin1_rd_data(ttlin1_rd_data),
// .ttlin2_rd_data(ttlin2_rd_data),
// .ttlin3_rd_data(ttlin3_rd_data),
// .ttlin4_rd_data(ttlin4_rd_data),
// .timecode_in_rd_data(timecode_in_rd_data),
// .genlock_in_rd_data(genlock_in_rd_data),
// .ttlout1_rd_data(ttlout1_rd_data), // ok
// .ttlout2_rd_data(ttlout2_rd_data), // ok
// .ttlout3_rd_data(ttlout3_rd_data), // ok
// .ttlout4_rd_data(ttlout4_rd_data), // ok
// .timecode_out_rd_data(timecode_out_rd_data),
// .genlock_out_rd_data(genlock_out_rd_data),
// .stm32_if_rd_data(stm32_if_rd_data),
// .debuger_rd_data(debuger_rd_data),
// .rd_data_out(reg_reader_bus_rd_data)
// );
/******************************************************************************* /*******************************************************************************
* TEST_SPI_REG * * TEST_SPI_REG *
*******************************************************************************/ *******************************************************************************/
zutils_register16 #( zutils_register16 #(
.REG_START_ADD(16'h00020)
.REG_START_ADD(`REG_ADD_OFF_FPGA_TEST)
) core_board_debug_led_reg ( ) core_board_debug_led_reg (
.clk(sys_clk), .clk(sys_clk),
.rst_n(rst_n), .rst_n(rst_n),
.addr(reg_reader_bus_addr), .addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data), .wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en), .wr_en(reg_reader_bus_wr_en),
.rd_data(reg_reader_bus_rd_data)
.rd_data(fpga_test_rd_data)
); );
@ -299,4 +295,28 @@ module Top (
// ); // );
rd_data_router rd_data_router_inst (
.addr(reg_reader_bus_addr),
.stm32_rd_data(stm32_rd_data),
.fpga_test_rd_data(fpga_test_rd_data),
.control_sensor_rd_data(control_sensor_rd_data),
.ttlin1_rd_data(ttlin1_rd_data),
.ttlin2_rd_data(ttlin2_rd_data),
.ttlin3_rd_data(ttlin3_rd_data),
.ttlin4_rd_data(ttlin4_rd_data),
.timecode_in_rd_data(timecode_in_rd_data),
.genlock_in_rd_data(genlock_in_rd_data),
.ttlout1_rd_data(ttlout1_rd_data), // ok
.ttlout2_rd_data(ttlout2_rd_data), // ok
.ttlout3_rd_data(ttlout3_rd_data), // ok
.ttlout4_rd_data(ttlout4_rd_data), // ok
.timecode_out_rd_data(timecode_out_rd_data),
.genlock_out_rd_data(genlock_out_rd_data),
.stm32_if_rd_data(stm32_if_rd_data),
.debuger_rd_data(debuger_rd_data),
.rd_data_out(reg_reader_bus_rd_data)
);
endmodule endmodule
Write Preview
Loading…
Cancel
Save